TIDUF18A October   2022  – February 2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1 CLLLC System Description
    1. 1.1 Key System Specifications
  8. 2 CLLLC System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations and System Design Theory
      1. 2.2.1 Tank Design
        1. 2.2.1.1 Voltage Gain
        2. 2.2.1.2 Transformer Gain Ratio Design (NCLLLC)
        3. 2.2.1.3 Magnetizing Inductance Selection (Lm)
        4. 2.2.1.4 Resonant Inductor and Capacitor Selection (Lrp and Crp)
      2. 2.2.2 Current and Voltage Sensing
        1. 2.2.2.1 VPRIM Voltage Sensing
        2. 2.2.2.2 VSEC Voltage Sensing
        3. 2.2.2.3 ISEC Current Sensing
        4. 2.2.2.4 ISEC TANK and IPRIM TANK
        5. 2.2.2.5 IPRIM Current Sensing
        6. 2.2.2.6 Protection (CMPSS and X-Bar)
      3. 2.2.3 PWM Modulation
  9. 3 Totem Pole PFC System Description
    1. 3.1 Benefits of Totem-Pole Bridgeless PFC
    2. 3.2 Totem-Pole Bridgeless PFC Operation
    3. 3.3 Key System Specifications
    4. 3.4 System Overview
      1. 3.4.1 Block Diagram
    5. 3.5 System Design Theory
      1. 3.5.1 PWM
      2. 3.5.2 Current Loop Model
      3. 3.5.3 DC Bus Regulation Loop
      4. 3.5.4 Soft Start Around Zero-Crossing for Eliminating or Reducing Current Spike
      5. 3.5.5 Current Calculation
      6. 3.5.6 Inductor Calculation
      7. 3.5.7 Output Capacitor Calculation
      8. 3.5.8 Current and Voltage Sense
  10. 4 Highlighted Products
    1. 4.1 C2000 MCU TMS320F28003x
    2. 4.2 LMG352xR30-Q1
    3. 4.3 UCC21222-Q1
    4. 4.4 AMC3330-Q1
    5. 4.5 AMC3302-Q1
  11. 5 Hardware, Software, Testing Requirements, and Test Results
    1. 5.1 Required Hardware and Software
      1. 5.1.1 Hardware Settings
        1. 5.1.1.1 Control Card Settings
      2. 5.1.2 Software
        1. 5.1.2.1 Opening the Project Inside Code Composer Studio
        2. 5.1.2.2 Project Structure
    2. 5.2 Testing and Results
      1. 5.2.1 Test Setup (Initial)
      2. 5.2.2 CLLLC Test Procedure
        1. 5.2.2.1 Lab 1. Primary to Secondary Power Flow, Open Loop Check PWM Driver
        2. 5.2.2.2 Lab 2. Primary to Secondary Power Flow, Open Loop CheckPWM Driver and ADC with Protection, Resistive Load Connected on Secondary
          1. 5.2.2.2.1 Setting Software Options for Lab 2
          2. 5.2.2.2.2 Building and Loading the Project and Setting up Debug Environment
          3. 5.2.2.2.3 Using Real-time Emulation
          4. 5.2.2.2.4 Running the Code
          5. 5.2.2.2.5 Measure SFRA Plant for Voltage Loop
          6. 5.2.2.2.6 Verify Active Synchronous Rectification
          7. 5.2.2.2.7 Measure SFRA Plant for Current Loop
        3. 5.2.2.3 Lab 3. Primary to Secondary Power Flow, Closed Voltage Loop Check, With Resistive Load Connected on Secondary
          1. 5.2.2.3.1 Setting Software Options for Lab 3
          2. 5.2.2.3.2 Building and Loading the Project and Setting up Debug Environment
          3. 5.2.2.3.3 Running the Code
          4. 5.2.2.3.4 Measure SFRA for Closed Voltage Loop
        4. 5.2.2.4 Lab 4. Primary to Secondary Power Flow, Closed Current Loop Check, With Resistive Load Connected on Secondary
          1. 5.2.2.4.1 Setting Software Options for Lab 4
          2. 5.2.2.4.2 Building and Loading the Project and Setting up Debug
          3. 5.2.2.4.3 Running the Code
          4. 5.2.2.4.4 Measure SFRA for Closed Current Loop
        5. 5.2.2.5 Lab 5. Primary to Secondary Power Flow, Closed Current Loop Check, With Resistive Load Connected on Secondary in Parallel to a Voltage Source to Emulate a Battery Connection on Secondary Side
          1. 5.2.2.5.1 Setting Software Options for Lab 5
          2. 5.2.2.5.2 Designing Current Loop Compensator
          3. 5.2.2.5.3 Building and Loading the Project and Setting up Debug
          4. 5.2.2.5.4 Running the Code
          5. 5.2.2.5.5 Measure SFRA for Closed Current Loop in Battery Emulated Mode
      3. 5.2.3 TTPLPFC Test procedure
        1. 5.2.3.1 Lab 1: Open Loop, DC
          1. 5.2.3.1.1 Setting Software Options for BUILD 1
          2. 5.2.3.1.2 Building and Loading Project
          3. 5.2.3.1.3 Setup Debug Environment Windows
          4. 5.2.3.1.4 Using Real-Time Emulation
          5. 5.2.3.1.5 Running Code
        2. 5.2.3.2 Lab 2: Closed Current Loop DC
          1. 5.2.3.2.1 Setting Software Options for BUILD 2
          2. 5.2.3.2.2 Designing Current Loop Compensator
          3. 5.2.3.2.3 Building and Loading Project and Setting Up Debug
          4. 5.2.3.2.4 Running Code
        3. 5.2.3.3 Lab 3: Closed Current Loop, AC
          1. 5.2.3.3.1 Setting Software Options for Lab 3
          2. 5.2.3.3.2 Building and Loading Project and Setting Up Debug
          3. 5.2.3.3.3 Running Code
        4. 5.2.3.4 Lab 4: Closed Voltage and Current Loop
          1. 5.2.3.4.1 Setting Software Options for BUILD 4
          2. 5.2.3.4.2 Building and Loading Project and Setting up Debug
          3. 5.2.3.4.3 Running Code
      4. 5.2.4 Test Results
        1. 5.2.4.1 Efficiency
        2. 5.2.4.2 System Performance
        3. 5.2.4.3 Bode Plots
        4. 5.2.4.4 Efficiency and Regulation Data
        5. 5.2.4.5 Thermal Data
        6. 5.2.4.6 PFC Waveforms
        7. 5.2.4.7 CLLLC Waveforms
  12. 6 Design Files
    1. 6.1 Schematics
    2. 6.2 Bill of Materials
    3. 6.3 Altium Project
    4. 6.4 Gerber Files
  13. 7 Software Files
  14. 8 Related Documentation
    1. 8.1 Trademarks
  15. 9 Terminology
  16. 10About the Author
  17. 11Revision History

3.1 Benefits of Totem-Pole Bridgeless PFC

All plug-in hybrid electric vehicles (PHEVs) require an onboard charger (OBC) between the power grid and the high-voltage battery pack located inside the vehicle. Implementing a power factor correction (PFC) converter is mandatory to connect directly to the power grid for AC/DC power conversion and maximize the real power that flows to the downstream DC/DC converters.

Conventional PFC converters implement a passive diode bridge for rectification, which is now known as a passive PFC technique. The advantages of such a scheme are: simple design, reliability, slow-system control loop, and low cost. However, the disadvantages are also very obvious: the passive components are heavy with a low-power factor and generate significant power losses, which results in bulky heat sinks and a lot of heat dissipation. Further investigation into the matter shows that an input bridge consumes approximately 2% of the input power at the low line of a wide mains application. If the designer can suppress one of the series diodes, then they can save 1% of the input power, which allows the efficiency to rise from 94% to 95% (Turchi; Dalal; Wang; Lenck 2014). Due to previously-mentioned drawbacks, the power rating of bridged traditional PFCs is limited under hundreds of watts, especially in a hybrid-electric vehicle (HEV) or electric vehicle (EV) where reduced space and weight are the key design parameters.

As a result, the trend continues to move toward a bridgeless architecture with the elimination of the traditional diode bridge. The OBC is based on a silicon power device and has limitations such as low efficiency, low power density, and high weight. With the advantages of the SiC MOSFET, the designer can greatly improve these limitations by utilizing the superior performance of fast switching, low reverse recovery charge, and a low RDS(ON).

Figure 3-1 shows the basic structure of the totem-pole bridgeless PFC boost rectifier. The component consists of a boost inductor, two high-frequency boost GaN or SiC switches (Labeled SiC1 and SiC2 in the diagram below), and two components for conducting current at the line frequency. The line frequency components can be two slow diodes, as Figure 3-1 shows. Side (A) shows two silicon diodes (D1 and D2). Side (B) shows that the use of Si1 and Si2 further increases the efficiency.

GUID-35888C74-7DB6-4B54-ABC6-2EA0E92705BB-low.gifFigure 3-1 Totem-Pole Bridgeless PFC Boost Converter Topology: (A) Diode for Line Rectification (B) MOSFET for Line Rectification

The inherent issue in the totem-pole PFC is the operation mode transition at the AC voltage zero-crossing. When the AC input changes from the positive half line to the negative half line at the zero-crossing, the duty ratio of the low-side high-frequency switch SiC2 changes from 100% to 0%, and the duty cycle of SiC1 changes from 0% to 100%. Because of the slow reverse recovery of the high-side diode (or body diode of the MOSFET), the voltage at the cathode of D2 cannot jump from ground to DC+ voltage instantly (this causes a large current spike). Because of this issue, the designer cannot use an Si MOSFET in a continuous-conduction mode (CCM) totem-pole PFC. Therefore SiC1 and SiC2 must be either gallium nitride (GaN) or SiC MOSFET field-effect transistors (FETs), which have a low reverse recovery, for TIDM-02013 we have chosen GaN FETs.

The biggest advantage of the totem-pole PFC is the reduced power losses in the conduction path. Table 3-1 shows the device comparison between a conventional PFC and a totem-pole PFC.

Table 3-1 Device Comparison of Conventional Bridged PFC and Totem-Pole Bridgeless PFC
PARAMETERLOW-FREQUENCY DIODESHIGH-FREQUENCY DIODESHIGH-FREQUENCY SWITCHESCONDUCTION PATHS
Conventional bridged PFCFourOneOneTwo low-speed diodes + one switch or (two low-speed diodes + one high-speed diode)
Totem-pole bridgeless PFCTwoZeroTwoOne high-speed GaN switch + one low-speed Si (or SiC) MOSFET

The following list summarizes the benefits of the totem-pole PFC:

  • Although the conventional PFC boost converter is the most popular topology, its efficiency suffers from the conduction losses of the front-end diode bridge rectifier and it is not bidirectional. A totem-pole PFC is inherently capable of bidirectional operation.
  • Bridgeless PFC boost converters greatly reduce the number of diodes, increase the power density, and increase the efficiency.
  • This PFC is superior in terms of: high efficiency, small common mode noise, small AC current ripple, small reverse recovery current, and fewer components.
  • The low reverse recovery charge of the GaN body diode and the low turn on resistance of the GaN FET make the converter an efficient and cost-effective solution for bidirectional onboard chargers.