TIDUF18A October   2022  – February 2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1 CLLLC System Description
    1. 1.1 Key System Specifications
  8. 2 CLLLC System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations and System Design Theory
      1. 2.2.1 Tank Design
        1. 2.2.1.1 Voltage Gain
        2. 2.2.1.2 Transformer Gain Ratio Design (NCLLLC)
        3. 2.2.1.3 Magnetizing Inductance Selection (Lm)
        4. 2.2.1.4 Resonant Inductor and Capacitor Selection (Lrp and Crp)
      2. 2.2.2 Current and Voltage Sensing
        1. 2.2.2.1 VPRIM Voltage Sensing
        2. 2.2.2.2 VSEC Voltage Sensing
        3. 2.2.2.3 ISEC Current Sensing
        4. 2.2.2.4 ISEC TANK and IPRIM TANK
        5. 2.2.2.5 IPRIM Current Sensing
        6. 2.2.2.6 Protection (CMPSS and X-Bar)
      3. 2.2.3 PWM Modulation
  9. 3 Totem Pole PFC System Description
    1. 3.1 Benefits of Totem-Pole Bridgeless PFC
    2. 3.2 Totem-Pole Bridgeless PFC Operation
    3. 3.3 Key System Specifications
    4. 3.4 System Overview
      1. 3.4.1 Block Diagram
    5. 3.5 System Design Theory
      1. 3.5.1 PWM
      2. 3.5.2 Current Loop Model
      3. 3.5.3 DC Bus Regulation Loop
      4. 3.5.4 Soft Start Around Zero-Crossing for Eliminating or Reducing Current Spike
      5. 3.5.5 Current Calculation
      6. 3.5.6 Inductor Calculation
      7. 3.5.7 Output Capacitor Calculation
      8. 3.5.8 Current and Voltage Sense
  10. 4 Highlighted Products
    1. 4.1 C2000 MCU TMS320F28003x
    2. 4.2 LMG352xR30-Q1
    3. 4.3 UCC21222-Q1
    4. 4.4 AMC3330-Q1
    5. 4.5 AMC3302-Q1
  11. 5 Hardware, Software, Testing Requirements, and Test Results
    1. 5.1 Required Hardware and Software
      1. 5.1.1 Hardware Settings
        1. 5.1.1.1 Control Card Settings
      2. 5.1.2 Software
        1. 5.1.2.1 Opening the Project Inside Code Composer Studio
        2. 5.1.2.2 Project Structure
    2. 5.2 Testing and Results
      1. 5.2.1 Test Setup (Initial)
      2. 5.2.2 CLLLC Test Procedure
        1. 5.2.2.1 Lab 1. Primary to Secondary Power Flow, Open Loop Check PWM Driver
        2. 5.2.2.2 Lab 2. Primary to Secondary Power Flow, Open Loop CheckPWM Driver and ADC with Protection, Resistive Load Connected on Secondary
          1. 5.2.2.2.1 Setting Software Options for Lab 2
          2. 5.2.2.2.2 Building and Loading the Project and Setting up Debug Environment
          3. 5.2.2.2.3 Using Real-time Emulation
          4. 5.2.2.2.4 Running the Code
          5. 5.2.2.2.5 Measure SFRA Plant for Voltage Loop
          6. 5.2.2.2.6 Verify Active Synchronous Rectification
          7. 5.2.2.2.7 Measure SFRA Plant for Current Loop
        3. 5.2.2.3 Lab 3. Primary to Secondary Power Flow, Closed Voltage Loop Check, With Resistive Load Connected on Secondary
          1. 5.2.2.3.1 Setting Software Options for Lab 3
          2. 5.2.2.3.2 Building and Loading the Project and Setting up Debug Environment
          3. 5.2.2.3.3 Running the Code
          4. 5.2.2.3.4 Measure SFRA for Closed Voltage Loop
        4. 5.2.2.4 Lab 4. Primary to Secondary Power Flow, Closed Current Loop Check, With Resistive Load Connected on Secondary
          1. 5.2.2.4.1 Setting Software Options for Lab 4
          2. 5.2.2.4.2 Building and Loading the Project and Setting up Debug
          3. 5.2.2.4.3 Running the Code
          4. 5.2.2.4.4 Measure SFRA for Closed Current Loop
        5. 5.2.2.5 Lab 5. Primary to Secondary Power Flow, Closed Current Loop Check, With Resistive Load Connected on Secondary in Parallel to a Voltage Source to Emulate a Battery Connection on Secondary Side
          1. 5.2.2.5.1 Setting Software Options for Lab 5
          2. 5.2.2.5.2 Designing Current Loop Compensator
          3. 5.2.2.5.3 Building and Loading the Project and Setting up Debug
          4. 5.2.2.5.4 Running the Code
          5. 5.2.2.5.5 Measure SFRA for Closed Current Loop in Battery Emulated Mode
      3. 5.2.3 TTPLPFC Test procedure
        1. 5.2.3.1 Lab 1: Open Loop, DC
          1. 5.2.3.1.1 Setting Software Options for BUILD 1
          2. 5.2.3.1.2 Building and Loading Project
          3. 5.2.3.1.3 Setup Debug Environment Windows
          4. 5.2.3.1.4 Using Real-Time Emulation
          5. 5.2.3.1.5 Running Code
        2. 5.2.3.2 Lab 2: Closed Current Loop DC
          1. 5.2.3.2.1 Setting Software Options for BUILD 2
          2. 5.2.3.2.2 Designing Current Loop Compensator
          3. 5.2.3.2.3 Building and Loading Project and Setting Up Debug
          4. 5.2.3.2.4 Running Code
        3. 5.2.3.3 Lab 3: Closed Current Loop, AC
          1. 5.2.3.3.1 Setting Software Options for Lab 3
          2. 5.2.3.3.2 Building and Loading Project and Setting Up Debug
          3. 5.2.3.3.3 Running Code
        4. 5.2.3.4 Lab 4: Closed Voltage and Current Loop
          1. 5.2.3.4.1 Setting Software Options for BUILD 4
          2. 5.2.3.4.2 Building and Loading Project and Setting up Debug
          3. 5.2.3.4.3 Running Code
      4. 5.2.4 Test Results
        1. 5.2.4.1 Efficiency
        2. 5.2.4.2 System Performance
        3. 5.2.4.3 Bode Plots
        4. 5.2.4.4 Efficiency and Regulation Data
        5. 5.2.4.5 Thermal Data
        6. 5.2.4.6 PFC Waveforms
        7. 5.2.4.7 CLLLC Waveforms
  12. 6 Design Files
    1. 6.1 Schematics
    2. 6.2 Bill of Materials
    3. 6.3 Altium Project
    4. 6.4 Gerber Files
  13. 7 Software Files
  14. 8 Related Documentation
    1. 8.1 Trademarks
  15. 9 Terminology
  16. 10About the Author
  17. 11Revision History
5.2.3.2.4 Running Code

The project is programmed to drive the inrush relay and clear the trip after a set amount of time, that is, autoStartSlew==100. The software is programmed to do so in the build level with DC. An input voltage must be applied after hitting run and before this autoslew counter reaches 100. If the counter reaches 100, before voltage is applied at the input, the code must be reset. For which the controller must be brought out of real time mode, a reset performed and restarted. Repeat the step from Section 5.2.3.2.3 of enabling real-time mode by hovering the mouse on the buttons on the horizontal toolbar and click the GUID-7488029A-9AD3-4B4F-836D-654BFF761294-low.png button.

Run the project by clicking GUID-0E577519-64C9-4C89-A28C-975CCF35D80F-low.png.

Apply an input voltage of approximately 50 V before the autoStartSlew reaches 100. As soon autoStartSlew reaches 100, the inrush relay is triggered, and PWM trip is cleared along with closing the current loop flag.

GUID-450C284B-FCDB-4AF4-9408-35D6AF70B7C3-low.gifFigure 5-35 Watch Expression, Build lab 2, DC After Closed Current Loop Operation Begins

The input current regulates approximately 1.5 A, and the output voltage boosts to approximately 193 V.

Slowly increase ac_cur_ref to 0.045, that is, 2.4-A input.

Slowly increase Vin = 120 V, and the output voltage will be greater than 370 V.

GUID-C25CEEA1-50DE-479F-B9ED-FBE3FDBAE2A2-low.gifFigure 5-36 Watch Expression, Build lab 2, DC After Closed Current Loop Operation Begins at Full Voltage

SFRA is integrated in the software of this build to verify that the designed compensator provides enough gain and phase margin by measuring on hardware. To run the SFRA, keep the project running, and navigate to <Install directory >\C2000Ware_DigitalPower_SDK_<version>\libraries\sfra\gui\SFRA_GUI.exe. The SFRA GUI appears.

Select the options for the device on the SFRA GUI. For example, for F28003x, select floating point. Click on Setup Connection. On the pop-up window, uncheck the boot on connect option, and select an appropriate COM port. Ensure Boot on Connect is deselected. Click OK. Return to the SFRA GUI, and click Connect.

The SFRA GUI connects to the device. An SFRA sweep can now be started by clicking Start Sweep. The complete SFRA sweep takes a few minutes to finish. Activity can be monitored by seeing the progress bar on the SFRA GUI and also checking the flashing of blue LED on the back on the control card that indicates UART activity. Once complete, a graph with the open loop plot appears. The frequency response data is also saved in the project folder under an SFRA data folder and is time stamped with the time of the SFRA run.

Additionally, the measured frequency response of the plant can be used to design the current compensator with compensation designer. <install Directory>\C2000Ware_DigitalPower_SDK_<version>\libraries\sfra\gui\CompDesigner.exe.

Choose SFRA Data for plant option on the GUI. This uses the measured plant information to design the compensator. This option can be used to fine tune the compensation. By default, the compensation designer points to the latest SFRA run. If a previous SFRA run plant information must be used, select the SFRAData.csv file by browsing to it by clicking on Browse SFRA Data. This action verifies the current compensator design.

Bring the system to a safe stop by bringing the input DC voltage down to zero. Ensure that the guiVbus comes down to zero as well.

Fully halting the MCU when in real-time mode is a two-step process. First halt the processor by using the Halt button on the toolbar (GUID-CEC61420-51B7-45ED-A276-0E2E645982AD-low.png) or by using Target → Halt. Then take the MCU out of real-time mode by clicking on GUID-F443C7B8-178A-4910-9044-9BC0FA9477F3-low.png. Finally, reset the MCU (GUID-8E8358D6-E5B2-4960-9A30-90C9B77C035B-low.png) .

Close the CCS debug session by clicking on Terminate Debug Session (Target → Terminate all).
GUID-38039C67-CB5D-4301-8BC2-3B268FD4BD48-low.png