TIDUF20 December   2022

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Auxiliary Power Strategy
      2. 2.2.2 High-Side N-Channel MOSFET
      3. 2.2.3 Stacked AFE Communication
    3. 2.3 Highlighted Products
      1. 2.3.1 BQ76942
      2. 2.3.2 LM5168
      3. 2.3.3 ISO1640
      4. 2.3.4 TCAN1042HV
      5. 2.3.5 THVD2410
      6. 2.3.6 TPS7A25
      7. 2.3.7 MSP430FR2155
      8. 2.3.8 TMP61
      9. 2.3.9 TPD2E007
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
    3. 3.3 Test Results
      1. 3.3.1 Cell Voltage Accuracy
      2. 3.3.2 Pack Current Accuracy
      3. 3.3.3 Auxiliary Power and System Current Consumption
      4. 3.3.4 Protection
      5. 3.3.5 Working Modes Transition
      6. 3.3.6 ESD Performance
  9. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  10. 5About the Author

3.2 Test Setup

Use the following procedures before running this design board. The design was constructed with 20S pack configurations. The board was tested using DC source and 4900-μF electrolytic capacitor in parallel to simulate the total pack. Twenty 1-kΩ resisters in series are used to divide the pack voltage and simulate 20s battery cells.

  • DC source 1 configurations: 72 V – 3 A
  • DC source 2 configurations: two channel 30 V – 0.5 A
  • Electronic load configurations: 60-V constant voltage (CV) mode

Figure 3-1 shows the charge process setup example.

Figure 3-1 Charge Setup

Figure 3-2 shows the discharge process setup example using the following conditions.

  • DC source configurations: 60 V – 20 A
  • Electronic load configurations: constant current (CC) mode
Figure 3-2 Discharge Setup