The ADS131M08 registers must be initialized to deliver measurement data from all 7 channels (the 8-th channel is unused but still has to be read out over SPI). This process is followed when the ADS131M08 is being first setup after the MSPM0G3507 MCU resets as well as each time calibration is performed.

Figure 3-1 ADC Initialization and Synchronization Process

The SPI module of the MSPM0+ MCU is configured for communication to the ADS131M08 device as a controller device that uses 4-wire mode (the chip-select signal is automatically asserted high and low by the SPI hardware module) and has a 19.87-MHz SPI clock that is derived from the MCU MCLK clock, divided by 4. After the SPI is setup, all interrupts are disabled and a reset command is sent from the MSPM0+ MCU to the ADS131M08 via SPI. Interrupts are then re-enabled and the MSPM0+ MCU sends commands to the ADS131M08 to configure the registers.

By sending write commands to the ADS131M08 registers, the following configuration is done:

• MODE register settings: 16-bit CCITT CRC used, 24-bit length for each word in the ADS131M08 packet, DRDY signal asserted on most lagging enabled channel, DRDY asserted high when conversion value is not available, DRDY asserted low when conversion values are ready
• GAIN1 register settings: PGA gain of 1 used for all four ADC channels
• CFG register settings: Current detection mode disabled
• CHx_CNG register settings (where x is the channel number)
  • 3-phase mode: All seven ADC channel inputs connected to external ADC pins and channel phase delay set to 0 for each channel (note that software phase compensation is used instead of ADS131M08 hardware phase compensation).
• CLOCK register settings: 512 OSR, all channels enabled, and high-resolution modulator power mode

After the ADS131M08 registers are properly initialized, the MSPM0+ MCU is configured to generate a port interrupt whenever a falling edge occurs on the DRDY pin, which indicates that the ADS131M08 has new measurement samples available.

The ADS131M08 modulator clock is derived from the clock fed to the CLKIN pin, which is output from the CLK_OUT output of the MSPM0+ MCU. The clock fed to the CLKIN pin of the ADS131M08 device is internally divided by two, to generate the ADS131M08 modulator clock. The sampling frequency of the ADS131M08 is therefore defined as shown in Equation 3.

where

• ƒ_S is the sampling rate
• ƒ_M is the modulator clock frequency
• ƒ_CLKIN is the clock fed to the ADS131M08 CLKIN pin
• OSR is the selected oversampling ratio

In this design, the CLK_OUT signal of the MSPM0+ MCU that is fed to the ADS131M08 CLKIN pin has a frequency of 8.192 MHz. The oversampling ratio is selected to be 512 with the appropriate register setting. As a result, the ADS131M08 modulator clock is set to 4.096 MHz and the sample rate is set to 8000 samples per second.

For a 3-phase system where each line-to-neutral voltage is measured, at least six ADC channels are necessary to independently measure three voltages and three currents. In this design, the following ADS131M08 channel mappings are used in software for the 3-phase configuration:

• AIN0P and AIN0N ADS131M08 ADC channel pins → Voltage V1 (Phase A Line-to-Neutral Voltage)
• AIN1P and AIN1N ADS131M08 ADC channel pins → Voltage V2 (Phase B Line-to-Neutral Voltage)
• AIN2P and AIN2N ADS131M08 ADC channel pins → Voltage V3 (Phase C Line-to-Neutral Voltage)
• AIN3P and AIN3N ADS131M08 ADC channel pins → Current I1 (Phase A Current)
• AIN4P and AIN4N ADS131M08 ADC channel pins → Current I2 (Phase B Current)
• AIN5P and AIN5N ADS131M08 ADC channel pins → Current I3 (Phase C Current)
• AIN6P and AIN6N ADS131M08 ADC channel pins → Current N (Neutral Current)
• AIN7P and AIN7N ADS131M08 ADC channel pins → unconnected, channel 7 data is always reported as 0x00 00 00 over SPI when ADS131M08 is 24-bit mode with channel 7 disabled