Two connectors to interface to MCUs with 3.3-V I/O are provided for easy evaluation on the 3-phase GaN-FET power stage. A 180-pin connector J1 and J2 fits the pin assignment of the C2000 controlCARDs, such as the F28379D controlCARD. The 5-V rail generated in the TIDA-010255 also provides power to the C2000 controlCARD.

The design supports clock edge delay compensation for the digital interface to delta-sigma modulators AMC1035 and AMC1306. The C2000 MCU, for example, generates a 20-MHz clock with ePWM6B (AMC1035) and ePWM7B (AMC1306) and a phase-shifted 20-MHz clock with the ePWM6A and ePWM7A. The ePWM6B or ePWM7B clock signal connects to the clock buffer and drives the AMC1306M05 or AMC1035 clock input. The ePWM6B, ePWM7B clock signal connects to the SDFM clock input, for example, SD1_C1 and SD1_C2. The phase shift between ePWM6A and ePWM6B or ePWM7A and ePWM7B can now be adjusted in software until an optimum setup and hold time of the bitstream data signal at the SDFM data input, for example, SD1_D1 versus the rising clock edge at SD1_C1 is measured.

The headers J6, J7, J8, J9, and J11 are generic to interface to other MCUs like a Sitara AM2631. For the pin assignment of the MCU connectors, see Section 4.1.2.