TIDUF29 October   2023

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Connectors
      2. 2.2.2 High-Speed Traces
      3. 2.2.3 Power Rails
    3. 2.3 Highlighted Products
      1. 2.3.1 DS560DF410
      2. 2.3.2 TPS62867
      3. 2.3.3 TPS7A52
      4. 2.3.4 TLV702
      5. 2.3.5 TXB0108
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
      1. 3.1.1 TX Output Eye Test
      2. 3.1.2 RX Link Test
    2. 3.2 Software Requirements
    3. 3.3 Test Setup
      1. 3.3.1 TX Output Eye Test
      2. 3.3.2 RX Link Test
    4. 3.4 Test Results
      1. 3.4.1 TX Output Eye Test
      2. 3.4.2 RX Link Test
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
      3. 4.1.3 Altium Project
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks

1 System Description

The TIDA-060043 reference design represents a front port application for a 56G retimer. This design provides a reference on how DS560DF410 can be implemented in a front port application and also allows for testing of DS560DF410 in front port applications.

This reference design can be used to test the following IEEE 802.3 specifications:

  • Clause 136: Physical Medium Dependent (PMD) sublayer and baseband medium, type 50GBASE-CR, 100GBASE-CR2, 200GBASE-CR4
  • Clause 92: Physical Medium Dependent (PMD) sublayer and baseband medium type 100GBASE-CR4
  • Annex 136A: TP0 and TP5 test point parameters and channel characteristics for 50GBASE-CR, 100GBASE-CR2, and 200GBASE-CR4
  • Annex 120E: Chip-to-module 200Gbps four-lane attachment unit interface (200GAUI-4 C2M) and 400Gbps eight-lane attachment unit interface (400GAUI-8 C2M)