TIDUF33 june   2023

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Current and Voltage Controller
      2. 2.2.2 High-Resolution PWM Generation
    3. 2.3 Highlighted Products
      1. 2.3.1 TMS320F280039
      2. 2.3.2 ADS131M08
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Software Requirements
      1. 3.2.1 Opening the Project Inside Code Composer Studio
      2. 3.2.2 Project Structure
      3. 3.2.3 Software Flow Diagram
    3. 3.3 Test Setup
      1. 3.3.1 Hardware Setup to Tune the Current and Voltage Loops
      2. 3.3.2 Hardware Setup to Test Bidirectional Power Flow
      3. 3.3.3 Hardware Setup for Current and Voltage Calibration
    4. 3.4 Test Procedure
      1. 3.4.1 Lab Variables Definitions
      2. 3.4.2 Lab 1. Open-Loop Current Control Single Phase
        1. 3.4.2.1 Setting Software Options for Lab 1
        2. 3.4.2.2 Building and Loading the Project and Setting up Debug Environment
        3. 3.4.2.3 Running the Code
      3. 3.4.3 Lab 2. Closed Loop Current Control Single Phase
        1. 3.4.3.1 Setting Software Options for Lab 2
        2. 3.4.3.2 Building and Loading the Project and Setting up Debug Environment
        3. 3.4.3.3 Running the Code
        4. 3.4.3.4 Current Calibration
      4. 3.4.4 Lab 3. Closed Loop Current Control Dual Phase
        1. 3.4.4.1 Setting Software Options for Lab 3
        2. 3.4.4.2 Building and Loading the Project and Setting up Debug Environment
        3. 3.4.4.3 Running the Code
      5. 3.4.5 Lab 4. Closed Loop Current and Voltage Control
        1. 3.4.5.1 Setting Software Options for Lab 4
        2. 3.4.5.2 Building and Loading the Project and Setting up Debug Environment
        3. 3.4.5.3 Running the Code
        4. 3.4.5.4 Voltage Calibration
    5. 3.5 Test Results
      1. 3.5.1 Current Loop Load Regulation Error
      2. 3.5.2 Voltage Loop Load Regulation Error
      3. 3.5.3 Voltage Transition at No Load
      4. 3.5.4 Transient Response at Start-Up
      5. 3.5.5 Bidirectional Current Switching Time
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Author

3.4.3.3 Running the Code

  1. To run this lab, make sure the hardware is set up as outlined in the previous section,Section 3.4.2.
  2. Run the project by clicking GUID-6A5E916F-7491-4EA1-8837-39F302DDDF73-low.gif from the menu bar.
  3. In the watch view, check if the BT2PH_InputVoltageSense_V is between 12 V –15 V in the Expression Window.
  4. Set the following parameters from the Expression Window:
    • Set the BT2PH_enableRelay_bool to 1 to enable the output relay.
    • BT2PH_userParam_V_I_ch1->iref_A = 15.0.
    • Set the BT2PH_userParam_V_I_ch1->en_bool = 1.
    • See Figure 3-25 for the Expression Window settings.
  5. BT2PH_measureMultiphase_V_I variable shows output current and voltage of the DC/DC converter. Isense1_A display value is close to iref_A setting with ±1 mA error.
  6. Figure 3-26 shows the SFRA setup to test the loop stability. Click on Run SFRA icon from the SYSCONFIG page. The SFRA GUI pops up.
  7. Select the options for the device on the SFRA GUI; for example, for F280039, select floating point. Click on setup connection. In the pop-up window, uncheck the boot-on-connect option and select an appropriate COM port. Click Ok. Return to the SFRA GUI and click the Connect button.
  8. The SFRA GUI connects to the device. A SFRA sweep can now be started by clicking Start Sweep. The complete SFRA sweep takes a few minutes to finish. Once complete, a graph with the measurement appears, as shown in Figure 3-19.
  9. The Frequency Response Data is saved in the project folder, under an SFRA Data Folder, and is time-stamped with the time of the SFRA run.
GUID-20230628-SS0I-TN8L-LZ29-KKWB5KCDF4GR-low.png Figure 3-17 Lab 2 Expression Window, Closed Loop
GUID-20230628-SS0I-NTND-SXL5-TND7GBGB5F8X-low.svg Figure 3-18 SFRA Setup for Closed-Loop Current Control
GUID-20230628-SS0I-W6WH-CW9P-2BRD9CK577C3-low.png Figure 3-19 Current Control Closed-Loop Frequency Response