TIDUF41A October   2023  – June 2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 TIOL112
      2. 2.3.2 MSPM0L1306
  9. 3Hardware, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
    3. 3.3 Test Results
      1. 3.3.1 TCD_PHYL_INTF_TRENHIGH and TCD_PHYL_INTF_TRENLOW
      2. 3.3.2 TCD_PHYL_INTF_UARTTRANSDELAY
      3. 3.3.3 TCD_PHYL_INTF_RESPONSETIME
      4. 3.3.4 TCD_PHYL_INTF_ISIRD
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Author
  12. 6Revision History

3.3.2 TCD_PHYL_INTF_UARTTRANSDELAY

To determine t2 time, the rising edges of the UART frames on the CQ line are observed to measure the time from one frame to the next. The time of the transmission of eleven bits is then subtracted so that only the time between two frames remain. The time is allowed to be between 0 and 3 times the bit time. In case of COM3, a maximum of 13µs is allowed.

TIDA-010263 T2 Measurement, First Device Response Start Bit to Second Start Bit Transition
Black = C/Q Line, Red = TIOL112 enable signal
Figure 3-19 T2 Measurement, First Device Response Start Bit to Second Start Bit Transition
Equation 1. 47.8µs – 11 × 4.34µs = 0.06µs, this equals 0.01 TBIT

A very low t2 time is expected, because the UART transmit buffer is reloaded automatically through direct memory access (DMA). The measurement is limited by the time resolution of the measurement.