TIDUF41A October   2023  – June 2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 TIOL112
      2. 2.3.2 MSPM0L1306
  9. 3Hardware, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
    3. 3.3 Test Results
      1. 3.3.1 TCD_PHYL_INTF_TRENHIGH and TCD_PHYL_INTF_TRENLOW
      2. 3.3.2 TCD_PHYL_INTF_UARTTRANSDELAY
      3. 3.3.3 TCD_PHYL_INTF_RESPONSETIME
      4. 3.3.4 TCD_PHYL_INTF_ISIRD
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Author
  12. 6Revision History

3.3 Test Results

Table 3-3 shows the physical layer tests according to the IO-Link test specification and the results of this reference design.

Table 3-3 Physical Layer Tests
ID NAME CONFIGURATION SPECIFICATION (CLAUSE) RESULT
SDCI_TC_0011 TCD_PHYL_INTF_ISD Measurement of the static power supply current at the L+ of the device see 5.3.2.3, Table 6 ISDIOLmax (VSD = 18V): 12.3mA ISDIOLmax (VSD = 30V): 13.6mA
SDCI_TC_0012 TCD_PHYL_INTF_ISIRD The current and communication of the device is monitored upon power-on: The device charge requirements and behavior at power-on are verified at minimum and maximum power supply conditions. see 5.3.2.3, Table 6 and 5.4.1, Table 10 QISD (VSD = 18V): < 3.5mA STARTUP count (VSD = 30V): 1 QISD (VSD = 18V): < 3.5mA STARTUP count (VSD = 30V): 1
SDCI_TC_0013 TCD_PHYL_INTF_VRESHIGH Driver capability of the device high-side driver.
Measurement of the voltage drop between supply L+ and C/Q(1) output under a load condition of 50mA.		 see 5.3.2.4, Table 7 VCQ (VSD = 18V): 0.13V VCQ (VSD = 30V): 0.13V
SDCI_TC_0014 TCD_PHYL_INTF_VRESLOW Driver capability of the device low-side driver.
Measurement of the voltage drop between negative supply L– and C/Q output at sink current of 50mA.		 see 5.3.2.4, Table 7 VCQ (VSD = 18V): 0.13V VCQ (VSD = 30V): 0.13V
SDCI_TC_0015 TCD_PHYL_INTF_IQQD Measurement of the quiescent current into C/Q in receive mode see 5.3.2.4, Table 7 ICQ (VSD = 18V, VID = 13V): < 1μA ICQ (VSD = 18V, VID = VSD): < 1μA ICQ (VSD = 30V, VID = 13V): < 1μA ICQ (VSD = 30V, VID = VSD): < 1μA
SDCI_TC_0016 TCD_PHYL_INTF_VTHHD Measurement of the threshold voltage for high level at the C/Q see 5.3.2.2, Table 5 VID at Transition 0 → 1 (VSD = 18V): 11.1V VID at Transition 0 → 1 (VSD = 30V): 11.1V
SDCI_TC_0017 TCD_PHYL_INTF_VTHLD Measurement of the threshold voltage for low level at the C/Q see 5.3.2.2, Table 5 VID at Transition 1 → 0 (VSD = 18V): 10.4V VID at Transition 1 → 0 (VSD = 30V): 10.4V
SDCI_TC_0018 TCD_PHYL_INTF_VHYSD Calculation of the hysteresis voltage at C/Q based on VTHHD and VTHLD see 5.3.2.2, Table 5 VHYSD (VSD = 18V): 0.7V VHYSD (VSD = 30V): 0.7V
SDCI_TC_0300 TCD_PHYL_INTF_VOLTRANGECQ The device behavior is tested after exposure to signal voltages exceeding the supply voltage see 5.3.2.2, Table 5, VIL and VIH Communication established
SDCI_TC_0027 TCD_PHYL_INTF_TRENHIGH The device releases the high-side output driver after successful reception of a wake-up request. Measure wake-up receive enable delay of the device with high signal at C/Q. The delay time is measured with a resistive voltage divider applied between L+ to C/Q and C/Q to L. see 5.3.3.3, Table 10 tREN at C/Q = high:
93µs
SDCI_TC_0028 TCD_PHYL_INTF_TRENLOW The device shall release the low-side output driver after successful reception of a wake-up request. Measure wake-up receive enable delay of the device with C/Q low. The delay time is measured with a resistive voltage divider applied between L+ to C/Q and C/Q to L. see 5.3.3.3, Table 10 tREN at C/Q = low:
94µs
SDCI_TC_0304 TCD_PHYL_INTF_UARTTRANSDELAY The delay time between two consecutive UART frames of a device reply message is measured. see A.3.4, equation (A.4) t2min: 0 TBIT t2max: 0 TBIT
SDCI_TC_0305 TCD_PHYL_INTF_RESPONSETIME The delay time between Master messages to device reply message (end of last UART frame to begin of first UART frame) is measured. see A.3.5, equation (A.5) tAmin: 4.25 TBIT tAmax: 4.25 TBIT
(1) C/Q = connection for communication (C) or switching (Q) signal (SIO)