TIDUF42 January   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Terminology
    2. 1.2 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 EnDAT 2.2 Interface
      2. 2.3.2 SDFM Interface
      3. 2.3.3 EPWM Interface
      4. 2.3.4 ICSS-PRU IEP
      5. 2.3.5 EtherCAT CiA402 Velocity Control
  9. 3System Design
  10. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
    2. 4.2 Software Requirements
    3. 4.3 Test Setup
    4. 4.4 Test Results
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
    2. 5.2 Tools and Software
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks
  12. 6About the Author

2.3.4 ICSS-PRU IEP

The following parameters apply for the IEP CMP setup:

  • 50-kHz EPWM cycle time
  • 50-kHz FOC loop update (In EnDAT ISR)
  • SYNC_OUT0 from EtherCAT Client (ICSSG1) to Sync EPWM clock
  • PRU_ICSSG0 IEP0 period is set to 6000 (300000000/50000)
    • It is also the EPWM period
    • PRU_ICSSG IEP0 based address is 0x3002E000
  • Setup CMP4 to trigger Sigma Delta encoded current feedback data sampling:
    • One CMP4 in per IEP or EPWM period: 10us (defined in gTestSdfmPrms.firstSampTrigTime)
    • Set in initPruSddf
  • Set up CMP3 and CMP6 to trigger EnDAT 2.2 encoded position feedback data sampling:
    • One CMP3 and CMP6 in per IEP or EPWM period: 3000 ns (defined in endat_periodic_interface.cmp3 and endat_periodic_interface.cmp6)
    • Set in endat_config_periodic_mode