TIDUF42 January   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Terminology
    2. 1.2 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 EnDAT 2.2 Interface
      2. 2.3.2 SDFM Interface
      3. 2.3.3 EPWM Interface
      4. 2.3.4 ICSS-PRU IEP
      5. 2.3.5 EtherCAT CiA402 Velocity Control
  9. 3System Design
  10. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
    2. 4.2 Software Requirements
    3. 4.3 Test Setup
    4. 4.4 Test Results
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
    2. 5.2 Tools and Software
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks
  12. 6About the Author

2.3.1 EnDAT 2.2 Interface

Table 2-1 shows the EnDAT 2.2 signal parameters.

Table 2-1 EnDAT 2.2 Signals (Two 4-wire encoders)
AM243x LP (PIN NUMBER) BP CONNECTORS BLDC BP SIGNAL NAME
GPIO1_78(C16) J8.73 VSENSOR1_SW_EN Encoder1 enable
PRG0_PRU1_GPO0(L5) J2.11 ENCODER_CLK1 Encoder1 clock
PRG0_PRU1_GPO2 (M2) J7.68 ENCODER_DATA_TX_EN1 Encoder1 TX enable
PRG0_PRU1_GPO1(J2) J7.67 ENCODER_DATA_TX1 Encoder1 TX
PRG0_PRU1_GPO13(T4) J8.71 ENCODER_DATA_RX1 Encoder1 RX
GPIO1_77(B17) J8.74 VSENSOR2_SW_EN Encoder2 enable
PRG0_PRU1_GPO6(F5) J7.69 ENCODER_CLK2 Encoder2 clock
PRG0_PRU1_GPO8(F4) J6.57 ENCODER_DATA_TX_EN2 Encoder2 TX enable
PRG0_PRU1_GPO12(P2) J8.72 ENCODER_DATA_TX2 Encoder2 TX
PRG0_PRU1_GPO11(P1) J7.70 ENCODER_DATA_RX2 Encoder2 RX

EnDat 2.2 Interrupts:

  • hwiPrms.intNum = ICSSG_PRU_ENDAT_INT_NUM | ICSSG_PRU_ENDAT_INT_NUM+2;
  • hwiPrms.callback = &pruEncoderIrqHandler | &pruEncoderIrqHandler2;
    • Motor Control Loop (FOC) one core per motor

EnDat 2.2 Input Data Buffer:

  • gEndatChInfo (in .gEncChData) in R5F_0_0 TCMB

ICSSG Pin MUX:

  • Mode (ICSSG_GPCFG0_REG[29-26]: PR1_PRU0_GP_MUX_SEL = 1h)
  • ICSSG_SA_MX_REG[7] G_MUX_EN = 0