TIDUF46 October   2023

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Multiplexer Network and Switch Strategy
      2. 2.2.2 Cell Balancing
      3. 2.2.3 Stacked AFE Communication
      4. 2.2.4 Isolated UART Interface to MCU
    3. 2.3 Highlighted Products
      1. 2.3.1 BQ79616
      2. 2.3.2 TMUX1308
      3. 2.3.3 TMUX1574
      4. 2.3.4 TMUX1102
      5. 2.3.5 TPS22810
      6. 2.3.6 ISO7742
      7. 2.3.7 TSD05C
      8. 2.3.8 ESD441
      9. 2.3.9 ESD2CAN24-Q1
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
    3. 3.3 Test Results
      1. 3.3.1 Cell Voltage Accuracy
      2. 3.3.2 Temperature Sensing Accuracy
      3. 3.3.3 Cell Voltage and Temperature Sensing Timings
      4. 3.3.4 Cell Balancing and Thermal Performance
      5. 3.3.5 Current Consumption
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Author

2.2.2 Cell Balancing

Figure 3-14 shows the cell balancing circuit.
GUID-20230925-SS0I-SL8R-0R1X-RCGTQLJG6R14-low.svg Figure 2-3 Cell Balancing Circuit

The design uses an internal field-effect transistor (FET) to achieve a 100-mA balancing current. Assuming the given condition: an initial CB voltage of 3.5 V, the final CB voltage is 3.3 V. To achieve 100-mA balancing current while the CB voltage is 3.5 V, Rcb6 = Rcb5 = 15 Ω is used.

The voltage across the Rcb5 also provides bias voltage to the external cell balancing NPN transistor. The Rcbe value can be determined based on the CB voltage and desired external cell balancing current. Rb needs to meet two conditions:

  1. Condition 1: NPN transistor work in the saturation region for a small heat dissipation area: ic < Coefficient × hfe × ib. hfe is the DC current transfer static ratio of the NPN transistor. The ic-hfe curve is found in the NPN transistor data sheet. While the ic equals the desired external cell balancing current, the corresponding maximum hfe in the whole temperature range can be used to meet condition 1. The coefficient is usually set to 2 to keep the NPN transistor in saturation region by a safe margin.
  2. Condition 2: UBE > UBE(on). UBE(on) is the base-emitter turn-on voltage. UBE(on) must be smaller than the voltage across the Rcb5 and as small as possible to enable an easy selection of Rb.

This design uses 300 Ω for Rb, which can support an external cell balancing current as large as 600 mA.