TIDUF46 October   2023

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Multiplexer Network and Switch Strategy
      2. 2.2.2 Cell Balancing
      3. 2.2.3 Stacked AFE Communication
      4. 2.2.4 Isolated UART Interface to MCU
    3. 2.3 Highlighted Products
      1. 2.3.1 BQ79616
      2. 2.3.2 TMUX1308
      3. 2.3.3 TMUX1574
      4. 2.3.4 TMUX1102
      5. 2.3.5 TPS22810
      6. 2.3.6 ISO7742
      7. 2.3.7 TSD05C
      8. 2.3.8 ESD441
      9. 2.3.9 ESD2CAN24-Q1
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
    3. 3.3 Test Results
      1. 3.3.1 Cell Voltage Accuracy
      2. 3.3.2 Temperature Sensing Accuracy
      3. 3.3.3 Cell Voltage and Temperature Sensing Timings
      4. 3.3.4 Cell Balancing and Thermal Performance
      5. 3.3.5 Current Consumption
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Author

3.2 Test Setup

Use the following procedures before running this design board. The design was constructed with 32s pack configurations. The board was tested using 24s-battery simulator to simulate the total pack. The bottom 16s cell channels are connected to the bottom BQ79616 device. The negative terminal of cell17 is connected to A2_CELL0 and the positive terminal of cell24 is connected to A2_TOP.

Figure 3-14 shows the BMU test setup.

GUID-20230925-SS0I-WRJF-CSTF-LDZCGBZVHHRK-low.svgFigure 3-1 BMU Test Setup