TIDUF61 May   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 TLV9002-Q1
      2. 2.2.2 TLV9034-Q1
      3. 2.2.3 TPS7B69-Q1
      4. 2.2.4 SN74HCS08-Q1
      5. 2.2.5 SN74HCS86-Q1
    3. 2.3 System Design Theory
      1. 2.3.1 TIDA-0020069 Operation
        1. 2.3.1.1 Constant Current Source
          1. 2.3.1.1.1 Design Goals
          2. 2.3.1.1.2 Design Description
          3. 2.3.1.1.3 Design Notes
          4. 2.3.1.1.4 Design Steps
        2. 2.3.1.2 Current Sensing
          1. 2.3.1.2.1 Design Goals
          2. 2.3.1.2.2 Design Description
          3. 2.3.1.2.3 Design Steps
        3. 2.3.1.3 Load Connections and Clamps
        4. 2.3.1.4 Modified Window Comparator
        5. 2.3.1.5 Digital Logic Gates
      2. 2.3.2 Status Indication
        1. 2.3.2.1 Normal Operation (Closed Connection) State
        2. 2.3.2.2 Open Connection State
        3. 2.3.2.3 Short-to-Battery State
        4. 2.3.2.4 Short-to-Ground State
  9. 3Hardware, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
    3. 3.3 Test Results
      1. 3.3.1 Normal Operation (Closed Connection) Test Results
      2. 3.3.2 Open Connection Test Results
      3. 3.3.3 Short-to-Battery Test Results
      4. 3.3.4 Short-to-Ground Test Results
      5. 3.3.5 Disable (Shutdown) Test Results
  10. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout Recommendations
      1. 4.3.1 Layout Prints
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
  11. 5Tools and Software
  12. 6Documentation Support
  13. 7Support Resources
  14. 8Trademarks
  15. 9About the Author
2.3.1.1.4 Design Steps

The transfer function of the circuit is:

Equation 1. Io = R 2 R 5 × (R 1 + R 2 ) × Vi
  1. Select resistors, R1 and R2, for the voltage divider at the input. These resistors are sized so that the common-mode input voltage seen at the amplifier non-inverting input terminal, Vi is less than the Lower Threshold voltage set in the Section 2.3.1.4 section. In the case of this design, the Lower Threshold was set to be 1.33V, so the value of Vi is set to 1V.
    Equation 2. V i n + = V i × R 2 R 1 + R 2  
    Equation 3. L e t   R 1 = 10 k Ω   ( S t a n d a r d   v a l u e ) ,   R 2 10 k Ω + R 2 = 1 V 5 V
    Equation 4. R 2 = 4 × R 1 = 40 k Ω
  2. Calculate the sense resistor, R5. Keeping the sense resistor sized as small as possible maximizes the load compliance voltage and reduces power dissipation. Set the voltage across the sense resistor to 1V. Limiting the voltage drop to 1V limits the power dissipated in the sense resistor to 100mW at full-scale output.
    Equation 5. L e t   V i n + = 1 V   a n d   I O = 10 m A R 5 = V i n + I O = 1 V 10 m A = 100 Ω
  3. Refer to TI Precision Labs for the design procedure on how to properly size the compensation components, R3, R4, and C1.