TIDUF63A December   2023  – June 2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 PV or Battery Input With DC/DC Converter
    2. 1.2 Isolation and CLLLC Converter
    3. 1.3 DC/AC Converter
    4. 1.4 Key System Specifications
  8. 2System Design Theory
    1. 2.1 Boost Converter Design
    2. 2.2 MPPT Operation
    3. 2.3 CLLLC Converter Design
      1. 2.3.1 Achieving Zero Voltage Switching (ZVS)
      2. 2.3.2 Resonant Tank Design
    4. 2.4 DC/AC Converter Design
  9. 3System Overview
    1. 3.1 Block Diagram
    2. 3.2 Design Considerations
      1. 3.2.1 DC/DC Converter
        1. 3.2.1.1 Input Current and Voltage Senses and MPPT
        2. 3.2.1.2 Inrush Current Limit
      2. 3.2.2 CLLLC Converter
        1. 3.2.2.1 Low-Voltage Side
        2. 3.2.2.2 High-Voltage Side
        3. 3.2.2.3 Modulation scheme
      3. 3.2.3 DC/AC Converter
        1. 3.2.3.1 Active Components Selection
          1. 3.2.3.1.1 High-Frequency FETs: GaN FETs
          2. 3.2.3.1.2 Isolated Power Supply
          3. 3.2.3.1.3 Low-Frequency FETs
        2. 3.2.3.2 Passive Components Selection
          1. 3.2.3.2.1 Boost Inductor Selection
          2. 3.2.3.2.2 Cx Capacitance Selection
          3. 3.2.3.2.3 EMI Filter Design
          4. 3.2.3.2.4 DC-Link Output Capacitance
        3. 3.2.3.3 Voltage and Current Measurements
    3. 3.3 Highlighted Products
      1. 3.3.1  TMDSCNCD280039C - TMS320F280039C Evaluation Module C2000™ MCU controlCARD™
      2. 3.3.2  LMG3522R050 - 650-V 50-mΩ GaN FET With Integrated Driver
      3. 3.3.3  LMG2100R044 - 100-V, 35-A GaN Half-Bridge Power Stage
      4. 3.3.4  TMCS1123 - Precision Hall-Effect Current Sensor
      5. 3.3.5  AMC1302 - Precision, ±50-mV Input, Reinforced Isolated Amplifier
      6. 3.3.6  AMC3330 - Precision, ±1-V Input, Reinforced Isolated Amplifier With Integrated DC/DC Converter
      7. 3.3.7  AMC1311 - High-Impedance, 2-V Input, Reinforced Isolated Amplifier
      8. 3.3.8  ISO6741 - General-Purpose Reinforced Quad-Channel Digital Isolators with Robust EMC
      9. 3.3.9  UCC21540 - Reinforced Isolation Dual-Channel Gate Driver
      10. 3.3.10 LM5164 - 100-V Input, 1-A Synchronous Buck DC/DC Converter with Ultra-low IQ
  10. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
    2. 4.2 Test Setup
      1. 4.2.1 DC/DC Test
      2. 4.2.2 DC/AC Test
    3. 4.3 Test Results
      1. 4.3.1 Input DC/DC Boost Results
      2. 4.3.2 CLLLC Results
      3. 4.3.3 DC/AC Results
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
    2. 5.2 Tools and Software
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks
  12. 6About the Author
  13. 7Revision History

Achieving Zero Voltage Switching (ZVS)

Transformers for resonant converters need to be designed to have enough magnetizing current to discharge output capacitance of the switches on both the sides. There are two conditions to be met. Make the energy stored in magnetizing and resonant inductors bigger than energy stored in output capacitance of switches on both sides. Also, the magnetizing current needs to be big enough to discharge capacitance of switches within a given dead time.

Equation 4. LM+LR×IM_PEAK22  CEQ×VIN22

where

  • IM_PEAK is maximum peak current in transformer
  • LM is the magnetizing inductance of the transformer
  • LR is the resonant tank inductance
  • VIN is the input voltage of the CLLLC converter
  • CEQ is the equivalent capacitance of the switching node
Equation 5. LMTDT4×CEQ×fsw

where

  • TDT is the duration of the dead time
  • CEQ is the equivalent capacitance of the switching node
  • LM is the magnetizing inductance of the transformer
  • fSW is the switching frequency of the CLLLC converter

The first condition (Equation 4) is the energy requirement and the second condition (Equation 5) is the slew rate requirement.

The peak magnetizing current is a half of the peak-to-peak value of magnetizing current.

Equation 6. IMPEAK=V4×(LM+LR)×fsw

The equivalent capacitance is the sum of capacitance on the LV side plus capacitance of the HV side reflected to the LV side:

Equation 7. CEQ=CP+CS'

where

  • CEQ is the equivalent capacitance of the switching node
  • CP is the capacitance of primary side switches
  • C'S is the capacitance of secondary side switches reflected to primary side

The reflected capacitance C'S can be calculated using transformer ratio:

Equation 8. Cs'=Cs×NSNP2

where

  • CS is the capacitance of secondary side switches
  • NS is the number of turns of the secondary winding
  • NP is the number of turns of the primary winding

The output capacitance of switches limit the maximum magnetizing inductance. Select switches as a trade-off between RDS(on) and COSS.