The proposed CLLLC converter has GaN switching devices on both sides of the transformer. This switches is needed to add bidirectional capability and to increase efficiency using synchronous rectification. The syncronous rectification (SR) is very important for GaN based designs because 3rd quadrant losses could be significant.

The controlling scheme for primary side and SR is important to keep ZVS and high efficiency. Depending on load the current through rectification devices can be discontinious and switches should be turned off when current reach zero. Early turn-off of the switch can cause additional 3rd quadrant losses. Late turn-off can cause current flowing from the secondary side back to the primary side. This current reduces turn-off current for primary side and causes non-ZVS switching on primary side. Addditionally the reverse current flow causes reactive power and lowers overall efficeiny.

To control SR timing transformer secondary side current a zero crossing needs to be detected. The current measurement needs to have very low propagation delay. Usually this is done with Rogowski coils, but in this design TCMS1133 Hall sensor was used. This current sensor has typical propagation delay of 50 ns. The output of the current sensor was routed to a CMPSS unit in the C2000 MCU. The CMPSS unit generates a trip signal for EPWM module at the moment when the secondary current comes close to zero. In the beginning of the switching cycle the current signal is noisy, therefore a blanking time is used to avoid false tripping.

Figure 3-9 CLLLC modulation scheme.

Both LLC1 and LLC2 are settled to 50% duty cycle. These EPWM modules starts with a zero phase-shift. During application soft-start (SS), the phase-shift increases slowly between both the units until the sequences arrive in the state as shown in Figure 3-9.

SR signals for H and L signals are turned on when TBCNT reaches zero and period respectively. EPWM corresponding to the SR has half-period phase shift to LLC2 so the rising edges of LLC2 and SR are in time. Than SR signals are forced in turn-on state during short blanking time. This time is needed to let the current signal stabilize after switching noise. When the blanking window ends, the EPWM module starts listening the tripping signal from the CMPSS module. If the current signal reaches a threshold, the SR signals are turned off before the end of cycle. In the end of the switching cycle the signal is turned off anyway and the blanking window is restarted for the next half-period.

The current threshold is selected with some advance to compensate delays in current sensing, isolator and turn-off process. This cause additional 3rd quadrant losses, but in resonant designs the current in the end of the switching cycle is close to zero and these losses are small.

During SS the SR is turned off and rectification uses 3rd quadrant conduction.

For operation in reverse direction the primary and secondary side changes their roles and CMPSS/EPWM signals should be re-initialized in C2000.