The LMG3522R030 which is a top-side cooled device, is also used for the AC/DC converter design. This GaN FET has integrated gate-drive and built-in protections. The gate drive speed can be configured by an external resistor. In the current board design, the AC/DC FETs can be divided into two power stages, let’s call them Power Stage A and Power Stage B, as seen in Figure 3-8.

Figure 3-8 Power Stages of DC/AC Converter

In each power stage, there exist two FETs which need isolation from the MCU. The control signal isolation is based on digital isolators ISO7762. The digital isolator is a six-channel, 4/2 device, and for this device the basic isolation version is used since that is enough for the system. Power to the digital isolator is supplied by the internally generated 5V from the LDO of the LMG3522R030 device. The power supply isolation is based on the UCC14131 which is a high isolation DC/DC power module and provides an isolated 12V supply for the GaN FET from the 12V power supply on the board. LMG3522R030 also has built-in junction temperature reporting. This temperature signal is isolated by using the same digital isolator. The temperature information can be used in the control MCU to thermally protect the converter when ambient temperature is high. Each digital isolator takes care of two FET’s temperature reporting, Fault/OC signals, and PWM signal. The dead-time between FETs on the same leg is kept to be 140ns to avoid shoot-through. The HS FETs have a configuration similar to that of the Bidirectional DC/DC converter with two FETs sourcing 12V from the magneto and the digital pins for both connected to the same digital isolator.

The switching frequency is quite high, there is importance to focus on the parasitic inductance and power loop. Reducing the effect of parasitic inductance reduces the voltage spike at the switching node. The routing for the switching node between the GaNs on the same switching node and the boost inductor has a very small loop area in the PCB layers and leads to small parasitic inductance and less ringing. The bottom layer is used for the switching nodes, which is kept relatively small but enough to have the approximate current carrying capability. Additionally, for the control circuitry of the switching node, polygons on inner layers 1 and 2 are exploited to extend the switching node and to provide a return path for the signals on top and bottom layer. Three ceramic capacitors in parallel help to reduce Equivalent Series Inductance (ESL) by a factor of three. The power loop between ceramic capacitors and the GaN is also made as small as possible. Both the power stages are designed to be symmetrical and the schematic and layout are kept as identical as possible.

Also important is to have a good DC Bus- or ground connection throughout the board. Also recommended to have a good polygon pour for DC Bus+, AC line and neutral current paths since these are carrying high currents. For signals on the top layer, the recommendation is to have a return layer on the inner layer 1, and for signals routed on the bottom the recommendation is to have a return path through inner layer 2. This helps in preserving the integrity of the signals.