LMG3522R030 is used for this stage. It is the 650V rated 30 mΩ GaN FET with integrated driver and has advanced power management features that include digital temperature reporting and fault detection for overcurrent, short-circuit, overtemperature, VDD UVLO, and high-impedance RDRV pin. The temperature of the GaN FET is reported through a variable duty-cycle PWM output and enables straightforward junction temperature reading at point of interest. An input EMI filter has been designed for differential noise rejection and to stay below the conducted emissions mask. High quality output ceramic capacitors and film capacitor is placed at the DC-link output to handle the current ripple. The inductor used is Bourns 145451. The schematic for one converter stage can be seen in Figure 3-2.

The switching frequency is quite high, so it is important to focus on the parasitic inductance and power loop. Reducing the effect of parasitic inductance reduces the voltage spike at the switching node. The routing for the switching node between the GaN, SiC diode, inductor has a very small loop area in the PCB layers and leads to small parasitic inductance and less ringing. Four capacitors in parallel help to reduce Equivalent Series Inductance (ESL) by a factor of four. The power loop between the diode, ceramic capacitors and the GaN is also made as small as possible. The layout for the LMG3522R030 is shown in Figure 3-3, where the switching node is highlighted in yellow and the power loop is marked with arrows. Notice, the SiC diode has a lot of vias underneath as can be seen in the layout. This is done in order to reduce the thermal resistance of the PCB by improving heat dissipation. Both the boost stages are designed to be symmetrical and the schematic and layout are kept as identical as possible.