TIDUF67 April 2024 – December 2024
Objectives for this build level:
In this build level, the board is executed in open loop mode with a fixed PWM duty cycle. The duty cycles are set to 50%. This build level verifies the sensing of feedback values from the power stage and also operation of the PWM gate driver and maintains there are no hardware issues. Additionally, calibration of input and output voltage sensing can be performed in this build level. During this process the motor must remain disconnected. The software block diagram of this build level is shown in Figure 4-12.