TIDUF68 February   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 LMG2100
      2. 2.3.2 INA241A
      3. 2.3.3 LMR38010
  9. 3System Design Theory
    1. 3.1 Three-Phase GaN Inverter Power Stage
      1. 3.1.1 LMG2100 GaN Half-Bridge Power Stage
    2. 3.2 Inline Shunt Precision-Phase Current Sensing With INA241A
    3. 3.3 Phase Voltage and DC Input Voltage Sensing
    4. 3.4 Power-Stage PCB Temperature Monitor
    5. 3.5 Power Management
      1. 3.5.1 48V to 5V DC/DC Converter
      2. 3.5.2 5V to 3.3V Rail
    6. 3.6 Interface to Host MCU
  10. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
      1. 4.1.1 TIDA-010936 PCB Overview
      2. 4.1.2 TIDA-010936 Jumper Settings
      3. 4.1.3 Interface to C2000™ MCU LaunchPad™ Development Kit
    2. 4.2 Software Requirements
    3. 4.3 Test Setup
    4. 4.4 Test Results
      1. 4.4.1 Power Management and System Power Up and Power Down
    5. 4.5 GaN Inverter Half-Bridge Module Switch Node Voltage
      1. 4.5.1 Switch Node Voltage Transient Response at 48V DC Bus
        1. 4.5.1.1 Output Current at ±1A
        2. 4.5.1.2 Output Current at ±10A
      2. 4.5.2 Impact of PWM Frequency to DC-Bus Voltage Ripple
      3. 4.5.3 Efficiency Measurements
      4. 4.5.4 Thermal Analysis
      5. 4.5.5 No Load Loss Test (COSS Losses)
  11. 5Design and Documentation Support
    1. 5.1 Design Files [Required Topic]
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
      3. 5.1.3 PCB Layout Recommendations
        1. 5.1.3.1 Layout Prints
      4. 5.1.4 Altium Project
      5. 5.1.5 Gerber Files
      6. 5.1.6 Assembly Drawings
    2. 5.2 Tools and Software
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks
  12. 6About the Author
  13. 7Recognition

4.5.5 No Load Loss Test (COSS Losses)

To see the effective parasitic capacitive losses, the TIDA-010936 PCB power losses were measured at zero load current with 50% PWM duty cycle and PWM switching frequencies from 8kHz to 80kHz, as shown in Equation 3.

Equation 3. P COSS l o s s = C O S S FET × V D C 2 × f P W M × 2

The simulation was done using COSS(TR) = 501pF from the LMG2100R044 data sheet, while adding an additional 80pF equivalent board related capacitance due to PCB and cabling parasitic capacitances.

To subtract the supply current offset on the TIDA-010936 at zero PWM switching, a first measurement was done without PWM switching, which yielded power losses of 0.765W at 48V supply without PWM switching. Then incremental increase of the power consumption starting from 8kHz to 80kHz PWM was printed against the simulated COSS power losses. In addition, the phase voltage resistor divider losses for sensing the three phase voltages (when switching) were subtracted from the measurement too, in order not to add these to the COSS power losses. The simulation is a good match with the measured COSS power losses.

GUID-20240220-SS0I-2F3F-JG7H-1VBDFZRRLD8Z-low.svg Figure 4-26 No Load (COSS) Power Losses at 48VDC vs PWM Frequency