TIDUF68 February 2024
The phase voltage for each phase and the DC link voltage, which is equal to the input voltage, are sensed through a resistor divider. Figure 3-4 shows an example of this for the DC-Link voltage (R19, R21) with a low-pass filter (C44) to attenuate the PWM carrier frequency. The phase voltage is scaled to 3.3V, assuming an absolute maximum voltage of 80V according to Equation 2.
The cutoff frequency (f – 3dB) of the low-pass filter was set to 1kHz, which provides around 32dB of attenuation to reject a 40kHz PWM carrier frequency and 40dB for a 100kHz PWM carrier frequency. The DC-link voltage is sensed through the same resistor divider (see Figure 3-4) and low-pass filtered to make sure all voltages have the same transient response and delay.