Large phased array radar and communication systems require many transceiver channels, each with high speed data converters at the core of the analog signal chain. Integrated RF sampling data converters are ideal devices to proliferate the required channels. Each one of those devices requires a high-speed sampling clock with excellent phase noise performance. Since the sampling clock frequency is the same for all the devices, a single high-performance clock signal can be distributed to all of the data converter devices. This reference design showcases a cascaded LMX1204 clock distribution chip to distribute one clock source input to 16 differential clock outputs. The design supports frequencies over 12GHz and introduces negligible degradation to the phase noise performance through the distribution. All clock signals are synchronized to maintain deterministic latency and ensure phase aligned outputs.

• 1-to-16 Clock Distribution Design
• Up to 12.8GHz Operation
• Very Low Phase Noise Performance
• 16 SysRef Outputs for JESD204B Data Converters
• Syncronized Outputs Maintain Deterministic Latency
• Optional Clock Divider or Clock Multiplier