TIDUF69 March   2024 LMX1204

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 LMX1204
      2. 2.3.2 TPS62913
      3. 2.3.3 TPS7A4700
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
    3. 3.3 Test Results
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Author

Design Considerations

RF sampling data converters require a low phase noise, high frequency clock signal. In a phased array system that employs many channels, the clock frequency is the same for each data converter device; hence, there is a need for distributing a single clock frequency. For the system to operate properly, all of the clock outputs must be phase aligned. Since phase noise performance is critical, the distribution network should not degrade phase noise performance compared to the original incoming signal.

The reference design demonstrates a cascaded LMX1204 device topology where the first level provides a 1:4 distribution. The second level takes each of those outputs and provides an additional 1:4 distribution, providing 16 outputs in total. The phase noise performance is not degraded within the distribution network. Since each output is independently buffered, all outputs maintain high signal levels negating any distribution losses through the network.