TIDUF69 March   2024 LMX1204

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 LMX1204
      2. 2.3.2 TPS62913
      3. 2.3.3 TPS7A4700
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
    3. 3.3 Test Results
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Author

LMX1204

The LMX1204 is a 1-to-4 clock distribution chip. The LMX1204 supports clock frequencies up to 12.8GHz and has very low additive jitter. All clock outputs are synchronized. In addition to the four high frequency outputs, there is an additional low frequency LOGICLK suitable for clocking FPGAs. Each output has an accompanying low frequency SysRef output for operation with data converters using the JESD204B digital interface. The SysRef signal can be generated internally or passed in as an input and re-clocked to the ouptuts. There is also an option to engage an input divide-down or multiply-up at the clock input.