The design is centered on the discrete DAC and ADC devices that support wide instantaneous bandwidth signals. The receive channels utilize active baluns to convert single-ended inputs to differential outputs to interface with the ADC input. The transmit channels utilize a different active balun to convert the differential interface to single-ended. Because industrial, -SEP, and -SP grade parts related to the data converters and active baluns are all in plastic with the same pin-out, a single PCB design supports all grade flavors.

The clocking design is on a daughter card that snaps onto the top of the data converter board. The clocking daughter card houses the LMK04832-SEP and the LMX2694-SEP. The LMK provides a low frequency reference to the LMX synthesizer. The LMK also provides the low frequency clock signals for the FPGA and the SysRef signals to the data converters and FPGA to support the JESD204B digital interface protocol. The LMX2694-SEP provides the low phase noise, high frequency sampling clock to the data converters. Because both DAC an ADC clocks come from the same device, the ADC clock must be an integer divider of the DAC clock.

A power design is on a daughter card that snaps into the bottom of the board. The power board provides all the power rails for the DAC, ADC, clock chips, RF active baluns, and current sensors. The approach generally provides LDOs on the sensitive analog rails to maintain the best performance. DC-DC converter provide direct power to less sensitive digital rails.