TIDUF70A April   2024  – June 2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Terminology
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 DAC39RF10-SEP
      2. 2.3.2 ADC12DJ5200-SEP
      3. 2.3.3 LMK04832-SEP
      4. 2.3.4 LMX2694-SEP
      5. 2.3.5 TPS7H4010-SEP
      6. 2.3.6 TPS7H1111-SEP
      7. 2.3.7 TPS7H1212-SEP
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Software Requirements
    3. 3.3 Test Setup
    4. 3.4 Test Procedure
    5. 3.5 Test Results
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Author
  12. 6Revision History

LMK04832-SEP

The LMK04832-SEP is a radiation tolerant, high performance clock conditioner with JESD204B/C support. The LNK04832-SEP has 14 clock outputs configurable as clock or SysRef outputs and has two PLLs (Phased Locked Loops). The first PLL operates as a jitter cleaner to lock a localized low jitter reference source, like a VCXO, to a low frequency system reference. The second PLL locks the internal VCO (Voltage Controlled Oscillator) to the low jitter reference. The device supports dual PLL, single PLL, or clock distribution modes.