The design is centered on the AFE7950-SP integrated RF sampling transceiver. The LMK04832-SEP provides a low frequency reference to the LMX2694-SEP. The LMK04832-SEP also provides the low frequency clock signals for the FPGA and the SysRef signals to the AFE and FPGA to support the JESD204B digital interface protocol. The LMX2694-SEP provides the low phase noise, high frequency sampling clock to the AFE. All of the receive channels utilize active baluns to convert single-ended inputs to differential outputs to interface with the ADC input. The lower frequency transmit channels also use active baluns to convert differential DAC output to single-ended. The high frequency transmit channels use a passive balun to convert differential to single-ended. Due to the small physical space allocation, the power supply is streamlined using DC-DC converters for most of the rails to minimize part count and maintain best efficiency.