TIDUF71A March   2024  – November 2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 AFE7950-SP
      2. 2.3.2 LMK04832-SEP
      3. 2.3.3 LMX2694-SEP
      4. 2.3.4 TRF0208-SEP
      5. 2.3.5 TPS7H4010-SEP
      6. 2.3.6 TPS73801-SEP
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Software Requirements
    3. 3.3 Test Setup
    4. 3.4 Hardware Configuration
    5. 3.5 Test Procedure
      1. 3.5.1 Initial TSW14J56 Setup
      2. 3.5.2 Reference Design Test Procedure
    6. 3.6 Test Results
      1. 3.6.1 TXA/B DAC Output Test Results
      2. 3.6.2 TXC/D DAC Output Test Results
      3. 3.6.3 RXA/B ADC Test Results
      4. 3.6.4 RXC/D ADC Test Results
      5. 3.6.5 FB2 ADC Test Results
    7. 3.7 Alternative Configurations
      1. 3.7.1 Internal AFE7950-SP PLL/VCO
        1. 3.7.1.1 The Easy Way - Internal PLL/VCO
        2. 3.7.1.2 The Proper Way - Internal PLL/VCO
      2. 3.7.2 Internal TCXO Operation
      3. 3.7.3 400MHz Bandwidth RX Configuration
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools
      1. 4.2.1 Latte Commands
      2. 4.2.2 Config Files
        1. 4.2.2.1 Latte Config Files
        2. 4.2.2.2 LMK / LMX Config Files
      3. 4.2.3 Troubleshooting
    3. 4.3 Hardware Identification Information
      1. 4.3.1 Rework Modifications
      2. 4.3.2 Reference Design Board Location Identification
      3. 4.3.3 FMC Interface Board Location Identification
    4. 4.4 Documentation Support
    5. 4.5 Support Resources
    6. 4.6 Trademarks
  11. 5About the Author
  12. 6Revision History

3.5.2 Reference Design Test Procedure

This is the basic test procedure for evaluating the reference design.

  • Engage power supply for the AFE7950-SP Reference Design
    • Set power supply voltage to 5.2V (headroom for voltage loss over cable)
    • Set current limit to 5.0 Amps (*** Critical: device draw over 4 Amps ***)
    • Turn on 5V power supply
    • Verify initial current is 1.25A +/-0.2 Amps
  • Setup LMK04832-SEP Low Frequency Clocks
    • Launch TICS Pro GUI
    • Verify jumper J6 location M on the interface board is *not* placed so the LMK device is programmed.
    • Select: Select Device > Clock Generator/Jitter Cleaner (Dual Loop) > LMK04832-SP
    • Select File > Load > LMK04832-SEP_TICsPro_122p88M_CLKINBypass_LMXRef.tcs
    • Supply Current increases to: 1.47A +/-0.2A
    • Debug/Verification tricks
      • LED D2 on the TSW14J56 starts flashing indicating that TSW14J56 is getting the proper clock
      • Scope Probe on C95 cap on LMK output to confirm 122.88MHz signal
  • Set-up LMX2694-SEP High Frequency Clock
    • Place jumper at J6 location M on the interface board to engage LMX programming
    • In TICS Pro, select: Select Device > PLL + VCO > LMX2694
    • Select File > Load > LMX2694-SEP_122p88Ref_122p88PFD_11796p48M.tcs
    • Supply Current increases to: 1.55A +/-0.2A
  • Set-up AFE7950-SP through Latte
    • Launch AFE79xx Latte
    • Select Setup.py; Press F5 to launch
      • Executes in about 8 seconds
      • Expect no errors
    • Select devInit.py; Press F5 to launch
      • Executes in about 30 seconds
      • Expect 1 error which can be ignored
      • Only needs to be launched once per new session
    • Select AFE7950-SP_12GClk_ExtClk.py; Press F5 to execute
      • Executes in 30 to 90 seconds
      • Expect no errors
      • Current fluctuates up and down during the bring-up programming
      • Supply current is: 3.95A +/- 0.3A
      • Debug trick:
        • If link is not established well, re-initiate a sync pulse with this Latte command: AFE.adcDacSync()
        • Verify LED D2 on TSW14J56 is still flashing
        • Verify supply current is at the expected level
  • Verify TX and RX Operation
    • After bring-up and no Latte errors, verify TX output tone at 2110MHz at around 4dBm.
      • Verify that cable loss at frequency of interest is accounted for
    • Switch HSDC Pro tab to ADC; Press Capture
      • Verify Channel selection is Channel 1 corresponding to RXA
      • Verify a successful FFT capture; verify LED D4 on TSW14J56 is flashing