TIDUF72 August   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
    2. 1.2 End Equipment
    3. 1.3 Electricity Meter
    4. 1.4 Power Quality Meter, Power Quality Analyzer
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Magnetic Tamper Detection With TMAG5273 Linear 3D Hall-Effect Sensor
      2. 2.2.2 Analog Inputs of Standalone ADCs
      3. 2.2.3 Voltage Measurement Analog Front End
      4. 2.2.4 Analog Front End for Current Measurement
    3. 2.3 Highlighted Products
      1. 2.3.1 AMC131M03
      2. 2.3.2 ADS131M02
      3. 2.3.3 MSPM0G1106
      4. 2.3.4 TMAG5273
      5. 2.3.5 ISO6731
      6. 2.3.6 TRS3232E
      7. 2.3.7 TPS709
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
      1. 3.1.1  Software Requirements
      2. 3.1.2  UART for PC GUI Communication
      3. 3.1.3  Direct Memory Access (DMA)
      4. 3.1.4  ADC Setup
      5. 3.1.5  Foreground Process
      6. 3.1.6  Formulas
        1. 3.1.6.1 Standard Metrology Parameters
        2. 3.1.6.2 Power Quality Formulas
      7. 3.1.7  Background Process
      8. 3.1.8  Software Function per_sample_dsp()
      9. 3.1.9  Voltage and Current Signals
      10. 3.1.10 Pure Waveform Samples
      11. 3.1.11 Frequency Measurement and Cycle Tracking
      12. 3.1.12 LED Pulse Generation
      13. 3.1.13 Phase Compensation
    2. 3.2 Test Setup
      1. 3.2.1 Power Supply Options and Jumper Setting
      2. 3.2.2 Electricity Meter Metrology Accuracy Testing
      3. 3.2.3 Viewing Metrology Readings and Calibration
        1. 3.2.3.1 Calibrating and Viewing Results From PC
      4. 3.2.4 Calibration and FLASH Settings for MSPM0+ MCU
      5. 3.2.5 Gain Calibration
      6. 3.2.6 Voltage and Current Gain Calibration
      7. 3.2.7 Active Power Gain Calibration
      8. 3.2.8 Offset Calibration
      9. 3.2.9 Phase Calibration
    3. 3.3 Test Results
      1. 3.3.1 Energy Metrology Accuracy Results
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
      3. 4.1.3 PCB Layout Recommendations
      4. 4.1.4 Layout Prints
      5. 4.1.5 Altium Project
      6. 4.1.6 Gerber Files
      7. 4.1.7 Assembly Drawings
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Authors

3.1.4 ADC Setup

The ADC131M03 and ADS131M02 device registers must be initialized to deliver proper measurement data on all relevant analog input channels. Figure 3-1 is followed at every start of the metrology application as well as each time the Calibrating and Viewing Results From PC metrology calibration procedure is performed.

The SPI module of the MSPM0+ MCU is configured as a controller device that uses 4-wire mode (the two chip-select signals are automatically asserted high and low by the SPI hardware module). After the SPI is set up, all interrupts are disabled and a reset pulse on the SYNC_RESET line is sent from the MSPM0+ MCU. Interrupts are then re-enabled and the MSPM0+ MCU sends SPI write commands sequential to ADS131M02 to configure the registers and then repeats the initialization step with AMC131M03:

  • MODE register settings: 16-bit CCITT CRC used, 24-bit length for each word in the ADS131M02 and AMC131M03 data packet, the DRDY signal is asserted on the most lagging enabled channel, DRDY is asserted high when the conversion value is not available, DRDY is asserted low when the conversion values are ready.
  • GAIN1 register settings for Voltage + Current: PGA gain = 1 used for the voltage channel, measuring the line-to-neutral or Phase A to Phase B voltage, PGA gain = 32 for the current channels on Phase A and Neutral or Phase B.
  • CFG register settings: Current detection mode is unused on ADS31M02 and is not supported on AMC131M03
  • CHx_CFG register settings (where x is the channel number: 0, 1 or 2)
    • one-phase mode: two ADC channel inputs connected to external ADC pins and the channel phase delay set to 0 for each channel (the software phase compensation in the SDK middleware is used instead of ADS131M02 or AMC131M03 hardware phase compensation)
  • CLOCK register settings: 1024 OSR, all channels enabled, and high-resolution modulator power mode

The MSPM0+ MCU is configured at start-up to generate a port interrupt whenever a falling edge occurs on any of the two DRDY pins, which indicate that new measurement samples are available.

TIDA-010944 ADC Initialization Procedure Figure 3-1 ADC Initialization Procedure

The ADC modulator clock is derived from the clock fed to the CLKIN pin which gets internally divided by two, to generate the ADC modulator clock. Equation 3 shows the definition of the sampling frequency of the ADC.

Equation 3. f S = f M O S R = f C L K I N 2 × O S R

where

  • ƒS is the sampling rate
  • ƒM is the modulator clock frequency
  • ƒCLKIN is the clock fed to the ADS131M02 and AMC131M03 CLKIN pin
  • OSR is the selected oversampling ratio

In this design, the M0_CLKOUT signal of the MSPM0+ MCU has a frequency of 8.192MHz. The oversampling ratio is selected to be 1024 with the appropriate register setting. As a result, the ADC modulator clock for both ADCs is set to 4.096MHz and the sample rate is set to 4000 samples per second.

For a single-phase system where each line-to-neutral voltage is measured, at least one ADS device is necessary to independently measure the phase voltage and current. In this design, the following ADC channel mappings are used in software for the single-phase and split-phase configuration:

  • AIN0P and AIN0N of ADS131M02 (U6) → Current I1 (Phase A current)
  • AIN1Pand AIN1N of ADS131M02 (U6) → Voltage V1 (Phase A line-to-neutral or Phase A line-to-phase B Voltage)
  • AIN0P and AIN0N of AMC131M03 (U2) → Current I2 (Phase B current)