TIDUF76 June   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Why use Radar?
    2. 1.2 TI Corner Radar Design
    3. 1.3 Key System Specification
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 AWRL1432 Single-Chip Radar Solution
      2. 2.3.2 AWRL1432BOOST-BSD Evaluation Module
      3. 2.3.3 TCAN4550-Q1 Integrated CAN-FD Controller and Transceiver
    4. 2.4 System Design Theory
      1. 2.4.1  Antenna Configuration
      2. 2.4.2  Chirp Configuration and System Performance
      3. 2.4.3  Data Path
      4. 2.4.4  Chirp Timing
      5. 2.4.5  Memory Allocation
      6. 2.4.6  Frame Reconfiguration
      7. 2.4.7  Vmax Extension
      8. 2.4.8  Group Tracker
      9. 2.4.9  Dynamic Clutter Removal
      10. 2.4.10 CAN-FD Transceiver
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Required Hardware and Software
      1. 3.1.1 Hardware
      2. 3.1.2 Software and GUI
    2. 3.2 Test Setup
    3. 3.3 Test Results
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks

2.4.10 CAN-FD Transceiver

The AWRL1432BOOST-BSD includes an integrated CAN-FD transceiver (TCAN4550-Q1), serving as a reference for system designs that require a second CAN-FD (in addition to the integrated CAN-FD interface on the AWRL1432). The TCAN4550-Q1 provides an interface between the CAN bus and the AWRL1432 through SPI, supporting both classic CAN and CAN-FD.

  • The TCAN4550-Q1 SPI signal pins are connected to the integrated SPIA interface of the AWRL1432.
  • The TCAN4550-Q1 device reset pin (RST) is connected to GPIO 6 of the AWRL1432 and is used to reset the device to the default settings and put the device into standby.
  • The TCAN4550-Q1 wake-up request pin (nWKRQ) is connected to GPIO 4 of the AWRL1432 and is used to serve as an enable for a regulator that does not use the INH pin to control voltage level. This is not used in the demo as the INH pin provides voltage to enable an external high voltage regulator.
  • The TCAN4550-Q1 interrupt pin (nINT) is connected to GPIO 5 of the AWRL1432 and is used to transmit all interrupt requests.
  • The TCAN4550-Q1 WAKE pin is connected to a user button (S6) and is used for high voltage device local wake-up (LWU) to transition the device into standby mode.
Because the TCAN4550-Q1 provides 2K bytes of MRAM that is fully configurable for TX/RX buffer/FIFO as needed based upon the system needs, implementing a second CAN-FD functionality does not add any overhead to the AWRL1432 memory.

The TCAN4550-Q1 is configured to the timing parameters shown in Table 2-5 for the BSD demo.

Table 2-5 CAN-FD Timing Parameters
Bit Rate (kbit/s) Sample Point (%) Prescaler TSEG1 TSEG2 SJW Tq (ns) Nq
Nominal 500 80 2 31 8 8 50 40
Data 2000 75 1 14 5 5 25 20

For more details on the TCAN4550-Q1 features, see the TCAN4550-Q1 data sheet.

For more details on the SPI to CAN-FD driver code, see the TCAN45xx Software User's Guide.