TIDUF78 May   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   Design Images
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
  9. 3System Design Theory
    1. 3.1 Hardware Design
    2. 3.2 Software Design
      1. 3.2.1 TMAG5170 SPI Frame
        1. 3.2.1.1 Serial Data In 32-Bit Frame
        2. 3.2.1.2 Serial Data Out 32-Bit Frame
      2. 3.2.2 TMAG5170 Register Configuration
      3. 3.2.3 SPI and Start-of-Conversion Timing
      4. 3.2.4 Linear Position Calculation
  10. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware
      1. 4.1.1 PCB Overview
      2. 4.1.2 MCU Interface Connector
    2. 4.2 Test Setup
    3. 4.3 Test Results
      1. 4.3.1 Magnetic Z and X Field Measurement
      2. 4.3.2 Linear Position Measurement
      3. 4.3.3 SPI Signal Measurement
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
      3. 5.1.3 PCB Layout
        1. 5.1.3.1 Layout Prints
        2. 5.1.3.2 Layout Guidelines
    2. 5.2 Tools and Software
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks
  12. 6About the Author

3.1 Hardware Design

Due to the high integration with the TMAG5170 3D Hall-effect sensor, the schematic is rather simple. The schematic is shown with Figure 3-1.

TIDA-060045 Quad TMAG5170 Schematic Figure 3-1 Quad TMAG5170 Schematic

The following description takes the U7 TMAG5170 as an example and applies to the remaining three TMAG5170 if not noted otherwise.

A 100nF decoupling capacitor C1 is added closed to the VCC and GND pin. An optional additional 1uF capacitor C2 is added in case of a more noise 3.3V supply, but was not populated in this design.

The TMAG5170 TEST pin, in the Altium schematic symbol named VCCIO, need to be tied to GND. The TMAG5170 nALERT pin is an input and is used to simultaneously trigger the start of the A/D converters with all four TMAG5170. The nALERT pin is routed from the connector J3-18 as daisy-chain from the first TMAG5170 (U7), through U10 and U11 to the last TMAG5170 (U8) for better signal integrity. A series line termination resistor option R5 at connector J3-18 was added as well as a far end parallel AC termination option with R9 and C8 (not populated by default) at U8 for test and validation. The SPI signals SCLK and SDO (MOSI) were routed as daisy-chain too, with a series line termination resistor and a far end parallel AC termination. For the SPI signal SDI (MISO), each SDO (MISO) output of the four TMAG5170 have a 33Ω termination, such as R1 with U7. The signals are routed in star topology and length matched from each TMAG5170 to a junction point where the signals are combined and routed to the connector J3-1. The SPI chip-select signals nC1, nC2, nC3, nC4 of each TMAG5170 where routed from the corresponding header J3 and each has a series line termination resistor option, such as R3 for U7.For SPI signal integrity tests, a GND test point TP1 through TP4 was added.

For SPI signal layout guidelines refer to chapter 5.

The test points TP1 through TP5 were not assembled on the final PCB to not disturb the TMAG5170 magnetic field measurement. A green LED D1 was added to indicate that the 3.3V supply is present.

The 3.3V input supply (+/10% tolerance) at the connecter J2-1 is routed to all four TMAG5170. A 0Ω resistor R4 is added for additional test and validation options. Either replace R4 with a ferrite bead for better RF noise rejection, if needed, or remove R4 to disconnect the 3.3V supply from the C2000 MCU Launch and use a separate 3.3V supply from a bench supply through test point TP5. In this reference design the 3.3V supply was used from the C2000 MCU LaunchPad.