TIDUF78 May   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   Design Images
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
  9. 3System Design Theory
    1. 3.1 Hardware Design
    2. 3.2 Software Design
      1. 3.2.1 TMAG5170 SPI Frame
        1. 3.2.1.1 Serial Data In 32-Bit Frame
        2. 3.2.1.2 Serial Data Out 32-Bit Frame
      2. 3.2.2 TMAG5170 Register Configuration
      3. 3.2.3 SPI and Start-of-Conversion Timing
      4. 3.2.4 Linear Position Calculation
  10. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware
      1. 4.1.1 PCB Overview
      2. 4.1.2 MCU Interface Connector
    2. 4.2 Test Setup
    3. 4.3 Test Results
      1. 4.3.1 Magnetic Z and X Field Measurement
      2. 4.3.2 Linear Position Measurement
      3. 4.3.3 SPI Signal Measurement
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
      3. 5.1.3 PCB Layout
        1. 5.1.3.1 Layout Prints
        2. 5.1.3.2 Layout Guidelines
    2. 5.2 Tools and Software
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks
  12. 6About the Author

5.1.3.2 Layout Guidelines

The layout of the SPI clock signal SCLK is shown in Figure 5-1. The SCLK is routed on the top layer in daisy chain from the first TMAG5170 (U7) to the last TMAG5170 (U8) with a serial line termination resistor and an optional far end AC parallel termination. The nALERT and the MOSI (TMAG5170 SDI) signals are routed the same way. A solid GND plane on the mid 1 layer below acts as a return GND.

TIDA-060045 SPI Clock (SCLK) Trace Routing Figure 5-1 SPI Clock (SCLK) Trace Routing

The individual SDO output (SPI MISO) of each TMAG5170 has a serial line termination resistor. The four SDO traces from each TMAG5170 are star routed with similar length before being merged into a single trace to connect to the host processor MISO input pin.

TIDA-060045 MISO Length Matched Star Topology Figure 5-2 MISO Length Matched Star Topology