TIDUF78 May   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   Design Images
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
  9. 3System Design Theory
    1. 3.1 Hardware Design
    2. 3.2 Software Design
      1. 3.2.1 TMAG5170 SPI Frame
        1. 3.2.1.1 Serial Data In 32-Bit Frame
        2. 3.2.1.2 Serial Data Out 32-Bit Frame
      2. 3.2.2 TMAG5170 Register Configuration
      3. 3.2.3 SPI and Start-of-Conversion Timing
      4. 3.2.4 Linear Position Calculation
  10. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware
      1. 4.1.1 PCB Overview
      2. 4.1.2 MCU Interface Connector
    2. 4.2 Test Setup
    3. 4.3 Test Results
      1. 4.3.1 Magnetic Z and X Field Measurement
      2. 4.3.2 Linear Position Measurement
      3. 4.3.3 SPI Signal Measurement
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
      3. 5.1.3 PCB Layout
        1. 5.1.3.1 Layout Prints
        2. 5.1.3.2 Layout Guidelines
    2. 5.2 Tools and Software
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks
  12. 6About the Author

3.2.2 TMAG5170 Register Configuration

The SPI on the TMS320F280049C MCU was setup as host with 10MHz SPI clock and two consecutive 16-bit SPI data transfers to support 32-bit frames. The serial clock was configured to low level before and after the SPI transfer. The SPI receive data (MISO) is latched on the rising SPI clock edge (SCLK) and the transmit data (MOSI) is transmitted on the falling clock edge.

After start-up the TMAG5170 registers were configured using the regular 32-Bit SDO read frame. Table 3-1 shows the default configuration with the N45 magnet used in this reference design.

Table 3-1 TMAG5170 Register Configuration
REGISTER OFFSET [HEX] VALUE [HEX] COMMENT
0h 0130h No averaging, sense magnetic temp coefficient 0.12%/deg C (NdBFe), active trigger mode
1h 0345h XZX channel enabled (pseudo-simultaneous sampling),Z range ±50mT, X range ±50mT
2h 0400h Conversion start at nALERT pulse (falling edge)
3h 0000h Default
4h 7D83h Default
5h 7D83h Default
6h 7D83h Default
7h 6732h Default
8h 0040h Read only
9h 0058h Read only
Ah 0000h Read only
Bh 7FD0h Read only
Ch 4500h Read only
Dh 0000h Read only
Eh 0300h Read only
Fh 0040h CRC enabled in SPI communication (default)
10h 0000h Reset OSC counter (default)
11h 0000h Default
12h 0000h Default
13h 0000h Read only
14h 0000h Read only

After the TMAG5170 register configuration was completed, a write command to each TMAG5170 to set the special 32-bit SDO frame. In this mode the field strength of the Z and X axis and CRC are transmitted a single 32-bit frame to reduce the overall latency.

Table 3-2 TMAG5170 Register Setting for Special 32-Bit SDO Frame
REGISTER OFFEST [HEX] VALUE [HEX] COMMENT
2h 0480h Conversion start at nALERT pulse (falling edge). Enable special 32-bit SDO frame (set bit 8)

For the absolute angle measurement using CORDIC, sensor data from the Z-axis and the X-axis are required to calculate an accurate angle. The magnetic field data collected at different times through the same signal chain with a single A/D converter introduces an error in the angle calculation. The TMAG5170 offers pseudo-simultaneous sampling data collection modes to eliminate this error. Figure 3-5 shows the example for the XZX channel mode (pseudo-simultaneous sampling mode) to collect XZX data and calculate the average X data from the dual X samples. Then the time stamps for the average X and Z sensor data are the same, assuming the X-axis signal frequency is significantly lower than the ADC sample rate.

TIDA-060045 TMAG5170 Pseudo-Simultaneous Sample Mode Figure 3-5 TMAG5170 Pseudo-Simultaneous Sample Mode