TIDUF83 September   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 DP83TC817S-Q1 (Automotive SPE PHY)
      2. 2.3.2 TPS629210-Q1 (3.3V Rail Buck Converter)
      3. 2.3.3 TPS7B8233-Q1 (3.3V VSLEEP Ultra-Low-IQ Low-Dropout Regulator)
      4. 2.3.4 TPS74701-Q1 (1.0V Rail Low-Dropout Regulator)
      5. 2.3.5 CDC6CE025000-Q1 (BAW Oscillator)
  9. 3System Design Theory
    1. 3.1 Ethernet PHY
      1. 3.1.1 Ethernet PHY Power Supply
      2. 3.1.2 Ethernet PHY Clock Source
    2. 3.2 Power Coupling Network
  10. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
    2. 4.2 Software Requirements
    3. 4.3 Test Setup
    4. 4.4 Test Results
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
    2. 5.2 Tools and Software
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks
  12. 6About the Author

2 System Overview

The system consists of this reference design, connected on one side through the expansion connector to a Jacinto 7 processor EVM and on the other side through one twisted-pair cable to a link partner as shown in Figure 2-1.

The Jacinto 7 EVM provides 5V power through the expansion connector to the buck converter and the LDO for 3.3V VSLEEP. The device also provides 12V through Jumper J6 to the differential mode inductor L7 to couple in power to the automotive Ethernet cable.