TIDUF83 September   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 DP83TC817S-Q1 (Automotive SPE PHY)
      2. 2.3.2 TPS629210-Q1 (3.3V Rail Buck Converter)
      3. 2.3.3 TPS7B8233-Q1 (3.3V VSLEEP Ultra-Low-IQ Low-Dropout Regulator)
      4. 2.3.4 TPS74701-Q1 (1.0V Rail Low-Dropout Regulator)
      5. 2.3.5 CDC6CE025000-Q1 (BAW Oscillator)
  9. 3System Design Theory
    1. 3.1 Ethernet PHY
      1. 3.1.1 Ethernet PHY Power Supply
      2. 3.1.2 Ethernet PHY Clock Source
    2. 3.2 Power Coupling Network
  10. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
    2. 4.2 Software Requirements
    3. 4.3 Test Setup
    4. 4.4 Test Results
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
    2. 5.2 Tools and Software
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks
  12. 6About the Author

2.3.1 DP83TC817S-Q1 (Automotive SPE PHY)

The DP83TC817-Q1 device is an IEEE 802.3bw automotive Ethernet physical layer transceiver. The device provides all physical layer functions needed to transmit and receive data, and xMII interface flexibility. DP83TC817-Q1 is compliant to Open Alliance EMC and interoperable specifications over unshielded single twisted-pair cable. DP83TC817-Q1 supports OA TC-10 low power sleep feature with wake forwarding for reduced system power consumption when communication is not required.

The DP83TC817-Q1 integrates IEEE 802.1AE line rate security with authentication and optional encryption support, to secure communication over the network. The PHY supports up to 16 secure association (SA) channels with automatic SAK rollover and extended packet numbering support. DP83TC817-Q1 offers ingress classification to filter the unwanted packets and supports WAN MACsec for end-to-end security.

DP83TC817-Q1 also integrates 1588v2 (802.1AS) to enable highly accurate time synchronization and hardware timestamping for ADAS applications. DP83TC817-Q1 also offers precise time stamping and synchronization with encrypted PTP packets.

DP83TC817-Q1 is footprint compatible to TI's 100BASE-T1 PHYs and 1000BASE-T1 PHYs enabling design scalability with a single board for different speeds and features.