TIDUF88 October   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Accuracy of Bus Voltage Measuring
      2. 2.2.2 Shunt Current Measuring
      3. 2.2.3 Insulation Impedance Monitor
    3. 2.3 Highlighted Products
      1. 2.3.1 BQ79731-Q1
      2. 2.3.2 TPSI2140-Q1
      3. 2.3.3 ISO7841
      4. 2.3.4 SN6507
      5. 2.3.5 TPS7B6950
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
    2. 3.2 Test Setup
    3. 3.3 Test Results
      1. 3.3.1 Bus Voltage Accuracy
      2. 3.3.2 Current Sensing Accuracy
      3. 3.3.3 Insulation Impedance Accuracy
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Author

2.2.1 Accuracy of Bus Voltage Measuring

Bus voltage measuring is a common function in high-voltage BMS. In Figure 2-1, there are three bus voltages including BAT+, RACK+, and RACK– to be measured. Bus voltage is used in the process of state-of-charge (SoC) estimation, precharge, wielding detection, and overvoltage protection. The design target accuracy is 0.5% while 1%, is required in GBT34131-2023.

TIDA-010272 High-Voltage Measuring Circuit Figure 2-3 High-Voltage Measuring Circuit

Figure 2-3 shows the high-voltage measuring circuit. The measuring circuit contains Rladder, Rsense, and ADC (BQ79731). Ileakage is the differential leakage current to ADC input of BQ79731. The accuracy of bus voltage measuring is affected by the error rate of Rladder (Rladder%), Rsense (Rsense%), Ileakage, and error of ADC (Veadc).

The actual bus voltage measured with the BQ79731 is Vbusmea, and Vbusmea = Vbus + Verror. Verror can be estimated as shown in Equation 1.

Equation 1. V e r r o r ≈ Vbus × R s e n s e % - R l a d d e r % 1 + R l a d d e r % + V e a d c × R l a d d e r + R s e n s e R s e n s e + I l e a k a g e × R l a d d e r + R s e n s e × 1 + R s e n s e %

Constant error is caused by Veadc and Ileakage which does not dominate the error if the Veadc and Ileakage is small enough. Veadc of BQ79731 VF and GPIO is ±3.16mV maximum from –40°C to 125°C. Ileakage of BQ79731 VF and GPIO is 20nA maximum from –40°C to 105°C. Considering 1500V BESS, voltage gain ≤ 400, and Rladder + Rsense ≤ 10MΩ. Then the constant error is less than 1.464V in 1500V ESS. This constant error is too small to be ignored or easily calibrated. The proportional error is related with Rsense% and Rladder%. Assuming the Rsense% and Rladder% are in range of ±1%. The worst case, the proportional error is in a range of ±2%. The proportional error can also be calibrated. If no calibration is used, the ±0.2% accuracy resistors must be used to achieve the ±0.4% accuracy of bus voltage measuring.

In this design, Rladder% and Rsense% are ±1%, Rladder is 6MΩ and Rsense is 16.63kΩ. This considers a basic isolation and creepage requirement of 7.6mm and the usage of four 1206 package Bourns® high-voltage resistors.