TIDUF96 October   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Power Topology
      2. 2.2.2 PCB and Form Factor
      3. 2.2.3 Antenna
    3. 2.3 Highlighted Products
      1. 2.3.1 AWRL1432BGAMFQ1
      2. 2.3.2 TPS628502-Q1
      3. 2.3.3 LMR43620-Q1
      4. 2.3.4 TLIN1021A-Q1
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Hardware Requirements
      1. 3.1.1 Getting Started With Hardware
        1. 3.1.1.1 Primary Power Up Option
          1. 3.1.1.1.1 Making the Connections in Primary Power Up Option
        2. 3.1.1.2 Secondary Power Up Option
          1. 3.1.1.2.1 Making the Connections in Secondary Power Up Option
        3. 3.1.1.3 Sense-on-Power (SOP)
        4. 3.1.1.4 AWRL1432 Initialization: Board Programming
    2. 3.2 Test Setup
    3. 3.3 Test Results
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
      3. 4.1.3 Layout Prints
      4. 4.1.4 Altium Project
      5. 4.1.5 Gerber Files
    2. 4.2 Tools and Software
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Authors

3.1.1.3 Sense-on-Power (SOP)

The AWRL1432 device has 3 different boot mode (SOP mode) configurations, Application mode (Functional mode), Device management mode (QSPI flashing mode), and Debug mode (Development mode). The SOP mode configurations shown in Table 3-1 must be exercised first. After the correct SOP mode is set, an nRESET must be issued to register the SOP setting.

Connector pins J2.5 and J2.6 are dedicated for SOP0 and SOP1, respectively. By default, SOP0 and SOP1 are pulled high in the design. Therefore, the device boots up in Debug mode when J2.5 and J2.6 are not connected externally. Connect J2.5 or J2.6 (or both) to GND (GND pins of the LP-XDS110 can be used) to switch between different SOP modes.

Table 3-1 Different SOP Modes
SOP MODE PMIC_CLK_OUT, TDO COMBINATION (SOP1, SOP0) CONNECTION REQUIRED FOR SOP1 CONNECTION REQUIRED FOR SOP0
SOP_MODE1 Device management mode (QSPI flashing mode) 00 GND GND
SOP_MODE2 Application mode (Functional mode) 01 GND NC
SOP_MODE4 Debug Mode (Development mode) 11 NC NC