TIDUF97 September   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 TMAG6180-Q1
      2. 2.3.2 MSPM0G3507
      3. 2.3.3 THVD1454
  9. 3System Design Theory
    1. 3.1 Hardware Design
      1. 3.1.1 Angle Sensor Schematic Design
      2. 3.1.2 MSPM0G3507 Schematic Design
      3. 3.1.3 RS485 Transceiver Schematic Design
      4. 3.1.4 Power Supply and Reference Voltage
    2. 3.2 Software Design
      1. 3.2.1 Angle Calculation Timing
      2. 3.2.2 Rotary Angle Calculation
      3. 3.2.3 Rotary Angle Error Sources and Compensation
      4. 3.2.4 Encoder Communication Interface
  10. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
      1. 4.1.1 PCB Overview
      2. 4.1.2 Encoder and JTAG Interface
      3. 4.1.3 Software Requirements
    2. 4.2 Test Setup
    3. 4.3 Test Results
      1. 4.3.1 AMR Sensor Sin and Cos Outputs Measurement
      2. 4.3.2 Static Angle Noise Measurement
      3. 4.3.3 Rotary Angle Accuracy Measurement
        1. 4.3.3.1 Impact of Airgap on Noise, Harmonics, and Total Angle Accuracy
      4. 4.3.4 RS485 Interface and Signal Integrity
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
      3. 5.1.3 PCB Layout
      4. 5.1.4 Altium Project Files
      5. 5.1.5 Gerber Files
      6. 5.1.6 Assembly Drawings
    2. 5.2 Tools and Software
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks
  12. 6About the Authors

3.1.2 MSPM0G3507 Schematic Design

TIDA-010947 MSPM0G3507 SchematicFigure 3-2 MSPM0G3507 Schematic

The ceramic decoupling capacitors C3 (10µF) and C4 (1µF) are placed across the VDD and VSS pins, and C1 (100nF), C2 (0.47uF) are placed across the VCORE and VSS pins. A ferrite bead FB1 is added between VDD and 3.3V power rail to avoid the high frequency digital current impacting the analog signal chain.

The nRST reset pin is pulled up to VDD with 47kΩ resistor R2 and 10nF pulldown capacitor C7. The SYSOSC frequency correction loop (FCL) circuit uses an external 100kΩ with 0.1% tolerance resistor R5 populated between the ROSC pin and VSS.

The MSPM0G3507 accepts an external reference to further improve the accuracy of the integrated ADC. In this design, an external 3.3V reference REF3533 is used and connected to the MSPM0G3507 VREF+ and VREF- pins. A 100nF decoupling capacitor (C10) is placed across VREF+ and VREF-.