TIDUF98A October 2024 – February 2025
The direct memory access (DMA) module supports communication over UART and SPI bus and enables packet transfers from and to MSPM0L2228 with minimal CPU bandwidth load.
Two DMA channels are used for communicating to the ADS131M03 over SPI Bus: DMA Channel 0 is used to send data to the ADS131M03 and DMA Channel 1 is used to simultaneously receive data from the ADS131M03. Once a complete packet has been received from the ADS131M03, a DMA done interrupt is generated and triggers the necessary post-transfer processing, such as CRC verification and data packet disassembly into voltage and current raw ADC values.
DMA Channel 2 is used for UART data reception from the PC GUI, the 14th byte of each DLT-645 packet contains the total packet length sent by the PC GUI (as packet length can change dynamically from packet to packet). The UART data is handled by HAL_startUARTDMAReceive() function, by setting the initial expected DMA length at 14 bytes. After decoding the byte 14, the UART DMA transfer length value gets updated, and now equals the rest of the DLT-645 protocol packet (total length - 14) in bytes. Thus the PC GUI packet can be received with two interrupts in total, as the DMA triggers again at the end of the UART packet.