TIDUFA8 November   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Terminology
    2. 1.2 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 IWRL6432
    3. 2.3 Design Considerations
      1. 2.3.1 Reference Design Features
    4. 2.4 IWRL6432 Reference Design Architecture
      1. 2.4.1 IWRL6432: BOM Optimized Design
        1. 2.4.1.1 Device Power Topology
      2. 2.4.2 Power Distribution Network
      3. 2.4.3 Internal LDOs
        1. 2.4.3.1 Enabling and Disabling Low Power Mode
        2. 2.4.3.2 1.4V Power Supplies: APLL and Synthesizer
          1. 2.4.3.2.1 APLL 1.4V
          2. 2.4.3.2.2 SYNTHESIZER 1.4V
        3. 2.4.3.3 1.2V Power Supplies
          1. 2.4.3.3.1 RF 1.2V Supply
        4. 2.4.3.4 RF 1.0V Power Supply
      4. 2.4.4 Component Selection
        1. 2.4.4.1 1.8V DC-DC Regulator
          1. 2.4.4.1.1 Need for Forced PWM Mode Switching
          2. 2.4.4.1.2 Importance of Spread Spectrum Clocking
        2. 2.4.4.2 3.3V Low Dropout Regulator
        3. 2.4.4.3 FLASH Memory
        4. 2.4.4.4 Crystal
  9. 3System Design Theory
    1. 3.1 Antenna Specification
      1. 3.1.1 Antenna Requirements
      2. 3.1.2 Antenna Orientation
      3. 3.1.3 Bandwidth and Return Loss
      4. 3.1.4 Antenna Gain Plots
    2. 3.2 Antenna Array
      1. 3.2.1 2D Antenna Array With 3D Detection Capability
      2. 3.2.2 1D Antenna Array With 2D Detection Capability
    3. 3.3 PCB
      1. 3.3.1 Via-in-Pad Elimination
      2. 3.3.2 Micro-Via Process Elimination
    4. 3.4 Configuration Parameters
      1. 3.4.1 Antenna Geometry
      2. 3.4.2 Range and Phase Compensation
      3. 3.4.3 Chirp Configuration
    5. 3.5 Schematic and Layout Design Conditions
      1. 3.5.1 Internal LDO Output Decoupling Capacitor and Layout Conditions for BOM Optimized Topology
        1. 3.5.1.1 Single-Capacitor Rail
          1. 3.5.1.1.1 1.2V Digital LDO
        2. 3.5.1.2 Two-Capacitor Rail
          1. 3.5.1.2.1 1.2V RF LDO
        3. 3.5.1.3 1.2V SRAM LDO
        4. 3.5.1.4 1.0V RF LDO
      2. 3.5.2 Best and non-Best Layout Practices
        1. 3.5.2.1 Decoupling Capacitor Placement
        2. 3.5.2.2 Ground Return Path
        3. 3.5.2.3 Trace Width of High Current Carrying Traces
        4. 3.5.2.4 Ground Plane Split
  10. 4Link Budget
  11. 5Hardware, Software, Testing Requirements and Test Results
    1. 5.1 Hardware Requirements
      1. 5.1.1 Connection to the USB to UART Bridges
      2. 5.1.2 USB Cable to Connect to Host PC
      3. 5.1.3 The Rx-Tx Attribution of RS232
    2. 5.2 Software Requirements
    3. 5.3 Test Scenarios
    4. 5.4 Test Results
      1. 5.4.1 Human Detection at 15 Meters in Boresight
      2. 5.4.2 Antenna Radiation Plots
      3. 5.4.3 Angle Estimation Accuracy in Azimuth Plane
      4. 5.4.4 Angle Resolution
  12. 6Design and Documentation Support
    1. 6.1 Design Files
      1. 6.1.1 Schematics
      2. 6.1.2 BOM
      3. 6.1.3 PCB Layout Recommendations
        1. 6.1.3.1 Layout Prints
    2. 6.2 Tools and Software
    3. 6.3 Documentation Support
    4. 6.4 Support Resources
    5. 6.5 Trademarks
  13. 7About the Authors
2.4.4.1.1 Need for Forced PWM Mode Switching

DC-DC switching converters use pulse width modulation (PWM) and or pulse frequency modulation (PFM) modes of switching. For light load conditions PFM switching scheme provides higher efficiency, however, injects a wide range of frequency components as ripple into the output. For higher load current requirement, PWM switching is required. Table 2-7 features the ripple specification for the radar device. This relates the very low ripple voltage that is allowable for the radar device.

Table 2-7 Noise and Ripple Specifications
FREQ (kHZ)Noise SpecificationRipple Specification
1.8V(µV/√Hz)1.2V (µV/√Hz)11.8V(mVpp)1.2V (mVpp)1
106.05744.9870.0351.996
1002.67726.8010.7602.233
2002.38828.3930.9553.116
5000.7579.5590.5041.152
10000.4191.1820.3790.532
20000.1791.2560.1530.561
50000.07980.6670.0790.297
100000.01780.1040.0170.046
(1) 1.2V noise or ripple specification is only for power optimized supply configurations. For BOM optimized topology 1.2V noise or ripple specification is not applicable.
Note:
  • Same 1.8V noise or ripple specification is applicable for the 1.8V supply in the BOM optimized topology
  • For latest information on noise and ripple spec please refer to IWRL6432 data sheet.

To keep the ripple introduced by the switching below the specifications, a second stage LC filter is deployed at the output of the DC-DC regulator in the design. However, if PFM mode of switching is used, the lower frequency (in kHz scale) ripple can pass through the filter and enter into the system, violating the above specifications. Therefore, forced PWM switching mode is recommended where the pulse width is fixed across the whole time of operation. This keeps the switching frequency fixed and the harmonics can be easily filtered out in the second stage filters.

If overall system power consumption needs to be optimized in device's deep sleep conditions where typically light load conditions are followed, auto mode of switching can be enabled. In this mode, depending on light load conditions PFM mode of switching is enabled to reduce power consumption of the DC regulator. Auto mode and forced PWM mode of switching can be altered using the MODE pin of the DC regulator. The MODE pin of the DC-DC regulator can be controlled by the device through a GPIO in a way that the DCDC regulator switches between auto mode and forced PWM mode depending on the device's deep sleep entry and exit. To get more detail on this please refer to Enabling PFM Mode for DCDC Converter.