TIDUFA8 November   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Terminology
    2. 1.2 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 IWRL6432
    3. 2.3 Design Considerations
      1. 2.3.1 Reference Design Features
    4. 2.4 IWRL6432 Reference Design Architecture
      1. 2.4.1 IWRL6432: BOM Optimized Design
        1. 2.4.1.1 Device Power Topology
      2. 2.4.2 Power Distribution Network
      3. 2.4.3 Internal LDOs
        1. 2.4.3.1 Enabling and Disabling Low Power Mode
        2. 2.4.3.2 1.4V Power Supplies: APLL and Synthesizer
          1. 2.4.3.2.1 APLL 1.4V
          2. 2.4.3.2.2 SYNTHESIZER 1.4V
        3. 2.4.3.3 1.2V Power Supplies
          1. 2.4.3.3.1 RF 1.2V Supply
        4. 2.4.3.4 RF 1.0V Power Supply
      4. 2.4.4 Component Selection
        1. 2.4.4.1 1.8V DC-DC Regulator
          1. 2.4.4.1.1 Need for Forced PWM Mode Switching
          2. 2.4.4.1.2 Importance of Spread Spectrum Clocking
        2. 2.4.4.2 3.3V Low Dropout Regulator
        3. 2.4.4.3 FLASH Memory
        4. 2.4.4.4 Crystal
  9. 3System Design Theory
    1. 3.1 Antenna Specification
      1. 3.1.1 Antenna Requirements
      2. 3.1.2 Antenna Orientation
      3. 3.1.3 Bandwidth and Return Loss
      4. 3.1.4 Antenna Gain Plots
    2. 3.2 Antenna Array
      1. 3.2.1 2D Antenna Array With 3D Detection Capability
      2. 3.2.2 1D Antenna Array With 2D Detection Capability
    3. 3.3 PCB
      1. 3.3.1 Via-in-Pad Elimination
      2. 3.3.2 Micro-Via Process Elimination
    4. 3.4 Configuration Parameters
      1. 3.4.1 Antenna Geometry
      2. 3.4.2 Range and Phase Compensation
      3. 3.4.3 Chirp Configuration
    5. 3.5 Schematic and Layout Design Conditions
      1. 3.5.1 Internal LDO Output Decoupling Capacitor and Layout Conditions for BOM Optimized Topology
        1. 3.5.1.1 Single-Capacitor Rail
          1. 3.5.1.1.1 1.2V Digital LDO
        2. 3.5.1.2 Two-Capacitor Rail
          1. 3.5.1.2.1 1.2V RF LDO
        3. 3.5.1.3 1.2V SRAM LDO
        4. 3.5.1.4 1.0V RF LDO
      2. 3.5.2 Best and non-Best Layout Practices
        1. 3.5.2.1 Decoupling Capacitor Placement
        2. 3.5.2.2 Ground Return Path
        3. 3.5.2.3 Trace Width of High Current Carrying Traces
        4. 3.5.2.4 Ground Plane Split
  10. 4Link Budget
  11. 5Hardware, Software, Testing Requirements and Test Results
    1. 5.1 Hardware Requirements
      1. 5.1.1 Connection to the USB to UART Bridges
      2. 5.1.2 USB Cable to Connect to Host PC
      3. 5.1.3 The Rx-Tx Attribution of RS232
    2. 5.2 Software Requirements
    3. 5.3 Test Scenarios
    4. 5.4 Test Results
      1. 5.4.1 Human Detection at 15 Meters in Boresight
      2. 5.4.2 Antenna Radiation Plots
      3. 5.4.3 Angle Estimation Accuracy in Azimuth Plane
      4. 5.4.4 Angle Resolution
  12. 6Design and Documentation Support
    1. 6.1 Design Files
      1. 6.1.1 Schematics
      2. 6.1.2 BOM
      3. 6.1.3 PCB Layout Recommendations
        1. 6.1.3.1 Layout Prints
    2. 6.2 Tools and Software
    3. 6.3 Documentation Support
    4. 6.4 Support Resources
    5. 6.5 Trademarks
  13. 7About the Authors

3.4.1 Antenna Geometry

As discussed in Section 3.2, different spatial positioning of the Tx and Rx antennas can produce different virtual antenna arrays. The relative position of these virtual antenna elements are necessary for determining the angle of arrival of the target objects. For this reason, the internal processing chain of the radar device needs to have the virtual antenna geometry information to provide angle information about the detection space.

This particular information, in a certain format, can be fed to the processing chain with the configuration file. There is a specific field in the configuration file called antGeometryCfg, where the antenna geometry information can be stated. Following is the format for the inputs of this command and an example of antGeometryCfg entries for the two antenna configurations associated with this reference design.


TIDEP-01033 Virtual Antenna Index for IWRL6432FCCSP Reference Design 2D Antenna Variant

Figure 3-25 Virtual Antenna Index for IWRL6432FCCSP Reference Design 2D Antenna Variant

Antenna geometry command for 2D antenna variant: antGeometryCfg 1 0 1 1 1 2 0 3 0 4 0 5 2.418 2.418

This line can be pasted in the configuration file.

Example configuration for motion detect:

sensorStop 0

antGeometryCfg 1 0 1 1 1 2 0 3 0 4 0 5 2.418 2.418

channelCfg 7 3 0

chirpComnCfg 8 0 0 256 4 28 0

chirpTimingCfg 6 63 0 75 60

frameCfg 2 0 200 64 250 0

guiMonitor 2 1 0 0 0 1 0 0 0 0 0

sigProcChainCfg 32 2 1 0 4 4 0 15

cfarCfg 2 8 4 3 0 12.0 0 0.5 0 1 1 1

aoaFovCfg -60 60 -40 40

rangeSelCfg 0.1 12.0

clutterRemoval 1

compRangeBiasAndRxChanPhase 0.0 1.00000 0.00000 -1.00000 0.00000 1.00000 0.00000 -1.00000 0.00000 1.00000 0.00000 -1.00000 0.00000

adcDataSource 0

adcLogging 0

lowPowerCfg 1

factoryCalibCfg 1 0 40 0 0x1ff000

mpdBoundaryBox 1 0 1.48 0 1.95 0 3

mpdBoundaryBox 2 0 1.48 1.95 3.9 0 3

mpdBoundaryBox 3 -1.48 0 0 1.95 0 3

mpdBoundaryBox 4 -1.48 0 1.95 3.9 0 3

sensorPosition 0 0 1.44 0 0

minorStateCfg 5 4 40 8 4 30 8 8

majorStateCfg 4 2 30 10 8 80 4 4

clusterCfg 1 0.5 2

baudRate 1250000

sensorStart 0 0 0 0


TIDEP-01033 Virtual Antenna Index for IWRL6432FCCSP Reference Design 1D Antenna Variant

Figure 3-26 Virtual Antenna Index for IWRL6432FCCSP Reference Design 1D Antenna Variant

Antenna geometry command for 1D antenna variant: antGeometryCfg 0 0 0 1 0 2 0 3 0 4 0 5 2.418 2.418

This line can be pasted in the configuration file.

Example configuration for motion detect:

sensorStop 0

antGeometryCfg 0 0 0 1 0 2 0 3 0 4 0 5 2.418 2.418

channelCfg 7 3 0

chirpComnCfg 8 0 0 256 4 28 0

chirpTimingCfg 6 63 0 75 60

frameCfg 2 0 200 64 250 0

guiMonitor 2 1 0 0 0 1 0 0 0 0 0

sigProcChainCfg 32 2 1 0 4 4 0 15

cfarCfg 2 8 4 3 0 12.0 0 0.5 0 1 1 1

aoaFovCfg -60 60 -40 40

rangeSelCfg 0.1 12.0

clutterRemoval 1

compRangeBiasAndRxChanPhase 0.0 1.00000 0.00000 -1.00000 0.00000 1.00000 0.00000 -1.00000 0.00000 1.00000 0.00000 -1.00000 0.00000

adcDataSource 0

adcLogging 0

lowPowerCfg 1

factoryCalibCfg 1 0 40 0 0x1ff000

mpdBoundaryBox 1 0 1.48 0 1.95 0 3

mpdBoundaryBox 2 0 1.48 1.95 3.9 0 3

mpdBoundaryBox 3 -1.48 0 0 1.95 0 3

mpdBoundaryBox 4 -1.48 0 1.95 3.9 0 3

sensorPosition 0 0 1.44 0 0

minorStateCfg 5 4 40 8 4 30 8 8

majorStateCfg 4 2 30 10 8 80 4 4

clusterCfg 1 0.5 2

baudRate 1250000

sensorStart 0 0 0 0

Note: Respective command line is necessary to add within any configuration, before sending the same to device, otherwise the angle of arrival calculated by the processing chain can be erroneous.

There are in total, 14 entries in the command antGeometryCfg. The first 12 entries specify the spatial position of the virtual antennas sequentially, according to the respective row index and column index, shown in Figure 3-26. For example, consider the first two entries that define position of virtual antenna 0. For 2D antenna variant, row and column index for virtual antenna 0 are "1" and "0", whereas for 1D antenna variant, row and column index for virtual antenna 0 are "0" and "0". Both the cases are reflected in the first two entries of the respective antGeometryCfg commands. In the same way the spatial positions of each of the other five virtual antennas are entered afterward in the following set of entries.

The last 2 entries define the unit length in the virtual antenna array space, for example, the antenna spacing between azimuth columns and antenna spacing between elevation rows, in mm. In this case, the antenna spacing for both the directions are equal to λ/2, which is 2.418mm, where λ (wavelength) is computed based on 62GHz as the center frequency of the chirp configuration.