TIDUFA8 November   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Terminology
    2. 1.2 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 IWRL6432
    3. 2.3 Design Considerations
      1. 2.3.1 Reference Design Features
    4. 2.4 IWRL6432 Reference Design Architecture
      1. 2.4.1 IWRL6432: BOM Optimized Design
        1. 2.4.1.1 Device Power Topology
      2. 2.4.2 Power Distribution Network
      3. 2.4.3 Internal LDOs
        1. 2.4.3.1 Enabling and Disabling Low Power Mode
        2. 2.4.3.2 1.4V Power Supplies: APLL and Synthesizer
          1. 2.4.3.2.1 APLL 1.4V
          2. 2.4.3.2.2 SYNTHESIZER 1.4V
        3. 2.4.3.3 1.2V Power Supplies
          1. 2.4.3.3.1 RF 1.2V Supply
        4. 2.4.3.4 RF 1.0V Power Supply
      4. 2.4.4 Component Selection
        1. 2.4.4.1 1.8V DC-DC Regulator
          1. 2.4.4.1.1 Need for Forced PWM Mode Switching
          2. 2.4.4.1.2 Importance of Spread Spectrum Clocking
        2. 2.4.4.2 3.3V Low Dropout Regulator
        3. 2.4.4.3 FLASH Memory
        4. 2.4.4.4 Crystal
  9. 3System Design Theory
    1. 3.1 Antenna Specification
      1. 3.1.1 Antenna Requirements
      2. 3.1.2 Antenna Orientation
      3. 3.1.3 Bandwidth and Return Loss
      4. 3.1.4 Antenna Gain Plots
    2. 3.2 Antenna Array
      1. 3.2.1 2D Antenna Array With 3D Detection Capability
      2. 3.2.2 1D Antenna Array With 2D Detection Capability
    3. 3.3 PCB
      1. 3.3.1 Via-in-Pad Elimination
      2. 3.3.2 Micro-Via Process Elimination
    4. 3.4 Configuration Parameters
      1. 3.4.1 Antenna Geometry
      2. 3.4.2 Range and Phase Compensation
      3. 3.4.3 Chirp Configuration
    5. 3.5 Schematic and Layout Design Conditions
      1. 3.5.1 Internal LDO Output Decoupling Capacitor and Layout Conditions for BOM Optimized Topology
        1. 3.5.1.1 Single-Capacitor Rail
          1. 3.5.1.1.1 1.2V Digital LDO
        2. 3.5.1.2 Two-Capacitor Rail
          1. 3.5.1.2.1 1.2V RF LDO
        3. 3.5.1.3 1.2V SRAM LDO
        4. 3.5.1.4 1.0V RF LDO
      2. 3.5.2 Best and non-Best Layout Practices
        1. 3.5.2.1 Decoupling Capacitor Placement
        2. 3.5.2.2 Ground Return Path
        3. 3.5.2.3 Trace Width of High Current Carrying Traces
        4. 3.5.2.4 Ground Plane Split
  10. 4Link Budget
  11. 5Hardware, Software, Testing Requirements and Test Results
    1. 5.1 Hardware Requirements
      1. 5.1.1 Connection to the USB to UART Bridges
      2. 5.1.2 USB Cable to Connect to Host PC
      3. 5.1.3 The Rx-Tx Attribution of RS232
    2. 5.2 Software Requirements
    3. 5.3 Test Scenarios
    4. 5.4 Test Results
      1. 5.4.1 Human Detection at 15 Meters in Boresight
      2. 5.4.2 Antenna Radiation Plots
      3. 5.4.3 Angle Estimation Accuracy in Azimuth Plane
      4. 5.4.4 Angle Resolution
  12. 6Design and Documentation Support
    1. 6.1 Design Files
      1. 6.1.1 Schematics
      2. 6.1.2 BOM
      3. 6.1.3 PCB Layout Recommendations
        1. 6.1.3.1 Layout Prints
    2. 6.2 Tools and Software
    3. 6.3 Documentation Support
    4. 6.4 Support Resources
    5. 6.5 Trademarks
  13. 7About the Authors
2.4.4.1.2 Importance of Spread Spectrum Clocking

Due to the periodicity of the switching signals, energy concentrates in one particular frequency and also in odd harmonics. This energy is radiated and therefore this is where a potential EMI issue arises. Radiated emission potentially causes emission failures. Conducted switching frequency causes issue is meeting ripple or noise spec and potentially cause ghost objects. Spread spectrum clocking (SSC) is a way to reduce both of the radiated and conducted emissions.

SSC is the variation of the frequency of a clock signal in a controlled way. In the frequency domain, the SSC reduces the peak amplitude of a clock signal by shifting the frequency. In other words, the energy of the clock is spread across small bandwidth with in the switching frequency.

Apart from this there is another reason for requiring SSC. The IF bandwidth of the IWRL6432 is 5MHz. The maximum switching frequency of the DCDC regulator is 4MHz. This means at least one harmonic of the switching frequency is going to fall inside the IF band. For this, the switching frequency needs to be as high as possible so that not more than one harmonic falls within the IF bandwidth. SSC is also required to spread the energy of that one harmonic falling inside the IF bandwidth to reduce the impact of the same.

Table 2-8 compares the device requirements for the 1.8V rail with TPS6285020M features.

Table 2-8 IWRL6432 1.8V Rail Requirements and Supporting Features of TPS6285020M
IWRL6432 Requirements for 1.8V RailTPS6285020M Features
Peak current requirement of 1.4A2A output current (continuous)
Low quiescent current15uA quiescent current
Forced PWM modeForced PWM or PFM/PWM operation using MODE
Spread spectrum clockingEnable or disable spread spectrum clocking (SSC) feature
Higher Switching Frequency (3.5MHz - 4MHz)Adjustable switching frequency: 1.8MHz to 4MHz
PGOOD feature Power-good output with window comparator
High efficiency>90% efficiency

Also, the TPS6285020M addresses minimum TON requirement for 5V input 1.2V output at 3.3MHz switching with SSC on.

The device has two control pins that determine the device operation mode. Following are the functionality and on-board configurations for the respective pins.

MODE or SYNC: When MODE or SYNC is set low, the device operates in PWM or PFM mode, depending on the output current. When set high, the device operates in forced PWM mode.

On-board configuration: Pulled up to VCC to enable forced PWM mode.

COMP or FSET: This pin allows to set three different parameters.

  1. Internal compensation settings for the control loop (two settings available)
  2. The switching frequency in PWM mode from 1.8MHz to 4MHz
  3. Enable or disable spread spectrum clocking (SSC)

A resistor from COMP or FSET to GND changes the compensation, the switching frequency and the SSC control.

On-board configuration: An 18kΩ resistor is connected from COMP or FSET to GND. This value of the resistor sets the device in the following configuration

  1. Switching frequency set to 3.3MHz
  2. Spread spectrum clocking (SSC) enabled
  3. Compensation setting 2 for best transient response.
Note:
  1. A second stage LC filter is required at the DCDC output to match the noise and ripple specifications and to avoid conducted switching frequency related issues.
  2. If switching frequency of the DC regulator is higher than the IF bandwidth (5MHz), the filter can be avoided.