TIDUFA8 November   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Terminology
    2. 1.2 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1 IWRL6432
    3. 2.3 Design Considerations
      1. 2.3.1 Reference Design Features
    4. 2.4 IWRL6432 Reference Design Architecture
      1. 2.4.1 IWRL6432: BOM Optimized Design
        1. 2.4.1.1 Device Power Topology
      2. 2.4.2 Power Distribution Network
      3. 2.4.3 Internal LDOs
        1. 2.4.3.1 Enabling and Disabling Low Power Mode
        2. 2.4.3.2 1.4V Power Supplies: APLL and Synthesizer
          1. 2.4.3.2.1 APLL 1.4V
          2. 2.4.3.2.2 SYNTHESIZER 1.4V
        3. 2.4.3.3 1.2V Power Supplies
          1. 2.4.3.3.1 RF 1.2V Supply
        4. 2.4.3.4 RF 1.0V Power Supply
      4. 2.4.4 Component Selection
        1. 2.4.4.1 1.8V DC-DC Regulator
          1. 2.4.4.1.1 Need for Forced PWM Mode Switching
          2. 2.4.4.1.2 Importance of Spread Spectrum Clocking
        2. 2.4.4.2 3.3V Low Dropout Regulator
        3. 2.4.4.3 FLASH Memory
        4. 2.4.4.4 Crystal
  9. 3System Design Theory
    1. 3.1 Antenna Specification
      1. 3.1.1 Antenna Requirements
      2. 3.1.2 Antenna Orientation
      3. 3.1.3 Bandwidth and Return Loss
      4. 3.1.4 Antenna Gain Plots
    2. 3.2 Antenna Array
      1. 3.2.1 2D Antenna Array With 3D Detection Capability
      2. 3.2.2 1D Antenna Array With 2D Detection Capability
    3. 3.3 PCB
      1. 3.3.1 Via-in-Pad Elimination
      2. 3.3.2 Micro-Via Process Elimination
    4. 3.4 Configuration Parameters
      1. 3.4.1 Antenna Geometry
      2. 3.4.2 Range and Phase Compensation
      3. 3.4.3 Chirp Configuration
    5. 3.5 Schematic and Layout Design Conditions
      1. 3.5.1 Internal LDO Output Decoupling Capacitor and Layout Conditions for BOM Optimized Topology
        1. 3.5.1.1 Single-Capacitor Rail
          1. 3.5.1.1.1 1.2V Digital LDO
        2. 3.5.1.2 Two-Capacitor Rail
          1. 3.5.1.2.1 1.2V RF LDO
        3. 3.5.1.3 1.2V SRAM LDO
        4. 3.5.1.4 1.0V RF LDO
      2. 3.5.2 Best and non-Best Layout Practices
        1. 3.5.2.1 Decoupling Capacitor Placement
        2. 3.5.2.2 Ground Return Path
        3. 3.5.2.3 Trace Width of High Current Carrying Traces
        4. 3.5.2.4 Ground Plane Split
  10. 4Link Budget
  11. 5Hardware, Software, Testing Requirements and Test Results
    1. 5.1 Hardware Requirements
      1. 5.1.1 Connection to the USB to UART Bridges
      2. 5.1.2 USB Cable to Connect to Host PC
      3. 5.1.3 The Rx-Tx Attribution of RS232
    2. 5.2 Software Requirements
    3. 5.3 Test Scenarios
    4. 5.4 Test Results
      1. 5.4.1 Human Detection at 15 Meters in Boresight
      2. 5.4.2 Antenna Radiation Plots
      3. 5.4.3 Angle Estimation Accuracy in Azimuth Plane
      4. 5.4.4 Angle Resolution
  12. 6Design and Documentation Support
    1. 6.1 Design Files
      1. 6.1.1 Schematics
      2. 6.1.2 BOM
      3. 6.1.3 PCB Layout Recommendations
        1. 6.1.3.1 Layout Prints
    2. 6.2 Tools and Software
    3. 6.3 Documentation Support
    4. 6.4 Support Resources
    5. 6.5 Trademarks
  13. 7About the Authors

2.4.1.1 Device Power Topology

The IWRL6432 can be operated in four different power topologies based on availability of the power supplies to the device with power consumption and BOM (cost) trade-off.

There are two topologies: power optimized topology and BOM optimized topology for IWRL6432. At most, three different supply voltages can be provided to the IWRL6432: 3.3V, 1.8V and 1.2V. The topologies are determined depending on whether the 1.2V is externally supplied to the device.

In power optimized topology, the 1.2V supply is externally provided. Higher current is provided by 1.2V rail which reduces the overall power consumption. This is why the topology is called power optimized. In BOM optimized topology, the 1.2V is NOT externally provided to the device. The on-chip LDOs generate the 1.2V supply there-by eliminating the need of external 1.2V rail. This is why this topology is called the BOM (bill of material) optimized topology.

The device supports two IO voltages: 3.3V and 1.8V. Thus, each of the power topologies can be further subdivided into two configurations depending on the IO voltage. At start-up, the device senses the number of external voltages provided and adjusts the IOs and determines whether the internal 1.2V supplies need to be activated. This creates incredible application based flexibility in terms of power topology and IO configuration.

The following tables summarize the power delivery to internal subsystems in different IO voltage operations under different topologies.

Table 2-2 Power Supply Rails Characteristics: Power Optimized 3.3V I/O Topology
SupplyDevice Blocks Powered From the Supply
3.3VDigital I/Os
1.8V

Synthesizer and APLL VCOs, crystal oscillator, IF

Amplifier stages, ADC

1.2VCore Digital and SRAMs, RF, VNWA
Table 2-3 Power Supply Rails Characteristics: Power Optimized 1.8V I/O Topology
SUPPLYDevice Blocks Powered From the Supply
1.8VDigital IOs, Synthesizer and APLL VCOs, crystal oscillator, IF Amplifier stages, ADC
1.2VCore Digital and SRAMs, RF, VNWA
Table 2-4 Power Supply Rails Characteristics: BOM Optimized 3.3V I/O Topology
SUPPLYDevice Blocks Powered From the Supply
3.3VDigital I/Os
1.8VSynthesizer and APLL VCOs, crystal oscillator, IF Amplifier stages, ADC
Table 2-5 Power Supply Rails Characteristics: BOM Optimized 1.8V I/O Topology
SUPPLYDevice Blocks Powered From the Supply
1.8VDigital IOs, Synthesizer and APLL VCOs, crystal oscillator, IF Amplifier stages, ADC
Note: In BOM optimized topology, digital cores, SRAM, RF and VNWA are all fed from the internally generated 1.2V rails.

In BOM optimized mode, the device can be operated using one rail (1.8V) or two rails (3.3V and 1.8V) depending upon 1.8V IO or 3.3V IO respectively.

In power optimized mode, the device can either be powered using two rails (1.8V and 1.2V) or with three rails (3.3V, 1.8V and 1.2V). During initial boot up, the device senses whether the external 1.2V supply is present or not and based on that determines if internally generated 1.2V LDOs are needed. With the 1.2V rail externally provided, the on-chip LDOs are not enabled in this case.

TIDEP-01033 BOM Optimized Mode Power Management (Left: Single Rail 1.8V I/O Topology, Right: Two Rails 3.3V I/O Topology)Figure 2-6 BOM Optimized Mode Power Management (Left: Single Rail 1.8V I/O Topology, Right: Two Rails 3.3V I/O Topology)
TIDEP-01033 Power Optimized Mode Power Management (Left: Two Rails 1.8V I/O Topology, Right: Three Rails 3.3V I/O Topology)Figure 2-7 Power Optimized Mode Power Management (Left: Two Rails 1.8V I/O Topology, Right: Three Rails 3.3V I/O Topology)

This reference design uses the BOM optimized topology (Figure 2-6) with provision to switch between 3.3V and 1.8V IO voltage operations.

The BOM optimized topology consumes little more power compared to that in the power optimized topology but optimizes the design cost significantly. Therefore, to optimize power consumption as well as cost, BOM optimized topology is used. For the power consumption comparison between different topologies, please refer to IWRL6432 Single-Chip 57- to 64GHz Industrial Radar Sensor, data sheet, section Typical Power Consumption Numbers.