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This document describes the operation and design of a flexible Successive Approximation Register (SAR) Analog to Digital Converter (ADC) model. The model was developed to be easily modifiable using SPICE parameters so that it can be used for simulating the behavior of many different SAR ADCs. By adjusting the parameters, this behavioral model can be modified to cover many different models of SAR ADCs. This document defines each parameter and shows how the parameter value can be determined from the device data sheet. Thus, if a model for a particular device is not available, the general model can be modified to cover most ADCs. Figure 1-1 shows the spice model with its associated parameter list. Various performance criteria such as input switching transients, noise, and offset can be modified by adjusting the model parameters. The first part of this document covers the internal operation of the model and how the external parameters can be set using data sheet criteria. The second part of this document covers ADC design optimization using the model. The final part of this document covers design performance verification using the model.
This section provides a simplified description of the internal operation of the model. Also, the meaning of the external parameters and selection of values based on data sheet criteria are covered.
A SAR ADC operates by sampling the input signal during the acquisition period and holding the signal during the conversion period. The sampling action is performed during the acquisition period by closing switch SW1 and allowing sampling Csh to charge via resistor Rsh. At the end of the acquisition period, the switch is opened and the input voltage is held for conversion. To achieve minimal distortion, the capacitor Csh needs to be fully settled at the end of the acquisition phase to properly measure the externally applied signal. The settling is dependent on amplifier bandwidth, the external RC filter, the internal sampling circuit, and the ADC timing. The model has a Vsamp output that shows the sampling behavior, and a Vsettling_error output that displays the difference between the sampled value and the steady state input signal. This settling analysis can be used to facilitate the selection of the amplifier and optimization of the external RC circuit. An input drive circuit optimization is covered in detail in Section 3.1. Figure 2-1 illustrates the ADC system design with the internal sample and hold circuit. Note that Rsh and Csh are parameters that can be adjusted according to the ADC data sheet. Most SAR ADC data sheets provide an input sampling stage equivalent circuit. This circuit provides values for Rsh and Csh.