Design Goals
Input | Output | Supply | ||||
---|---|---|---|---|---|---|
ViMin | ViMax | VoMin | VoMax | VCC | VEE | Vref |
0 V | 5 V | –12 V | +12 V | +15 V | –15 V | 5 V |
Design Description
This design is intended to translate a small unipolar signal to a wide bipolar signal. A common application is to translate a 5-V DAC output to a ±12-V bipolar signal. The document provides equations needed to calculate component values for other voltage range requirements. Important error sources are covered using calculations and simulation.
Design Notes
Specifications
Parameter | Design Goal | Simulated (Without Buffered Voltage Divider) |
Simulated (With Buffered Voltage Divider) |
---|---|---|---|
VoutMin | –12 V | –11.8 V | –11.95 V |
VoutMax | +12 V | +11.92 V | +11.99 V |
Bandwidth | 50 kHz | 48.5 kHz | 48.5 kHz |
Noise | N/A | 32.9 µVRMS | 24.2 µVRMS |
Design Steps
DC Transfer Characteristics
The following images show the DC Transfer function for the standard and buffered version of the circuit. Note that the buffered version is more accurate. Also note that the values selected in the buffered version, use the same ratios, but the magnitudes are adjusted. The buffered version decreased the feedback network impedance for better noise, and increased the divider network for better power dissipation. Note that the inaccuracy in the transfer function can be accounted for with a simple calibration (see the Calibration video).
AC Transfer Characteristics
The capacitor Cf sets the cutoff frequency to 100 kHz. This causes the gain of the amplifier to roll-off until gain is 1 V/V or 0 dB. At higher frequency the bandwidth limitations of the amplifier causes gain to roll-off again. The expected bandwidth of 50 kHz compares well to the simulated 48.5 kHz. Additional detail on bandwidth limitations are given in the Bandwidth video series.
Noise Simulation
Total noise is approximately 32.9 µVRMS. Peak-to-peak is approximately 6 × RMS = 197 µVpp. For more information on noise analysis and optimization see the Noise video series. Note that the noise of the buffered version is lower because the voltage divider uses lower resistor values which minimizes total noise.
Stability
This circuit is stable for capacitive loads from 0 pF to 120 pF. The analysis below shows 48.2°C of phase margin for a 120-pF load (45°C and better is considered stable). For more information on stability see the Stability video series.
Design Featured Devices and Alternative Parts
This design works with most amplifiers that accept high-voltage ±15-V supplies. Depending on the application the key parameters can be different. The following table shows three different options representing different categories of devices. Package-trimmed devices have good offset and offset drift by adjusting internal device resistors, zero-drift devices use an internal calibration to reduce offset and drift, and general-purpose are optimized for best cost. When using a zero-drift option, a best practice is to keep the total feedback impedance less than 10 kΩ (Rf || (Rg + R1 || R2) < 10 kΩ). This is recommended to avoid translating bias current into offset voltage. Click on the other possible devices link for a list of other options in the same category.
Device | Key Features | Other Possible Devices |
---|---|---|
OPA206 | 36-V supply, 3.6-MHz bandwidth, low noise (8 nV/√Hz), rail-to-rail output, 240-μA supply current, low offset 25 µV, 0.5 µV/˚C, e-trim™ op amp,with super-beta inputs and OVP |
36-V e-trim™ |
OPA182 | 36-V supply,
2-MHz bandwidth, rail-to-rail input to -V/Out, low
noise (8.8 nV/√Hz), low
offset 25 µV, 0.03 µV/˚C, zero-drift amplifier |
36-V zero-drift |
LM358B | 36-V supply, 1.2-MHz bandwidth, rail-to-rail input to -V, general-purpose | 36-V cost-optimized |
Design References
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