DAC8x11 2-V to 5.5-V, 80-μA, 14- and 16-Bit, Low-Power, Single-Channel, Digital-to-Analog Converters in SC70 Package
- SBAS439C August 2008 – July 2015 DAC8311 , DAC8411
  
  PRODUCTION DATA.

Full reading width

DATA SHEET

DAC8x11 2-V to 5.5-V, 80-μA, 14- and 16-Bit, Low-Power, Single-Channel, Digital-to-Analog Converters in SC70 Package

1 Features

Relative Accuracy:
- 1 LSB INL (DAC8311: 14-bit)
- 4 LSB INL (DAC8411: 16-bit)
microPower Operation: 80 μA at 2 V
Power-Down: 0.5 μA at 5 V, 0.1 μA at 2 V
Wide Power Supply: 2 V to 5.5 V
Power-On Reset to Zero Scale
Straight Binary Data Format
Low Power Serial Interface With Schmitt-Triggered Inputs: Up to 50 MHz
On-Chip Output Buffer Amplifier, Rail-to-Rail Operation
SYNC Interrupt Facility
Extended Temperature Range –40°C to 125°C
Pin-Compatible Family in a Tiny, 6-Pin SC70 Package

2 Applications

Portable, Battery-Powered instruments
Process Controls
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources

Simplified Schematic

3 Description

The DAC8311 (14-bit) and DAC8411 (16-bit) devices are low-power, single-channel, voltage output digital-to-analog converters (DAC). They provide excellent linearity and minimize undesired code-to-code transient voltages while offering an easy upgrade path within a pin-compatible family. All devices use a versatile, 3-wire serial interface that operates at clock rates of up to 50 MHz and is compatible with standard SPI™, QSPI™, Microwire, and digital signal processor (DSP) interfaces.

All devices use an external power supply as a reference voltage to set the output range. The devices incorporate a power-on reset (POR) circuit that ensures the DAC output powers up at 0 V and remains there until a valid write to the device occurs. The DAC8311 and DAC8411 contain a power-down feature, accessed over the serial interface, that reduces current consumption of the device to 0.1 μA at 2 V in power down mode. The low power consumption of these devices in normal operation makes it ideally suited for portable, battery-operated equipment. The power consumption is 0.55 mW at 5 V, reducing to 2.5 μW in power-down mode.

These devices are pin-compatible with the DAC5311, DAC6311, and DAC7311, offering an easy upgrade path from 8-, 10-, and 12-bit resolution to 14- and 16-bit. All devices are available in a small, 6-pin, SC70 package. This package offers a flexible, pin-compatible, and functionally-compatible drop-in solution within the family over an extended temperature range of –40°C to 125°C.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
DAC8311 DAC8411	SC70 (6)	2.00 mm × 1.25 mm

For all available packages, see the orderable addendum at the end of the data sheet.

4 Revision History

Changes from B Revision (May 2013) to C Revision

Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

Changes from A Revision (August, 2011) to B Revision

Changed all 1.8V to 2.0V throughout data sheetGo
Deleted 1.8-V Typical Characteristics sectionGo
Changed X-axis for Figure 35Go
Changed X-axis for Figure 36Go

Changes from * Revision (August, 2008) to A Revision

Changed specifications and test conditions for input low voltage parameterGo
Changed specifications and test conditions for input high voltage parameterGo

5 Device Comparison

Table 1. Related Devices

RELATED DEVICES	16-BIT	14-BIT	12-BIT	10-BIT	8-BIT
Pin and Function Compatible	DAC8411	DAC8311	DAC7311	DAC6311	DAC5311

Table 2. Package Information

PRODUCT	MAXIMUM RELATIVE ACCURACY (LSB)	MAXIMUM DIFFERENTIAL NONLINEARITY (LSB)
DAC8411	±8	±2
DAC8311	±4	±1

6 Pin Configuration and Functions

DCK Package

6-Pin SC70

Top View

Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
AV_DD/V_REF	4	I	Power Supply Input, +2 V to +5.5 V.
D_IN	3	I	Serial Data Input. Data is clocked into the 24-bit (DAC8411) or 16-bit (DAC8311) input shift register on the falling edge of the serial clock input.
GND	5	—	Ground reference point for all circuitry on the part.
SCLK	2	I	Serial Clock Input. Data can be transferred at rates up to 50 MHz.
SYNC	1	I	Level-triggered control input (active low). This is the frame sychronization signal for the input data. When SYNC goes low, it enables the input shift register and data are transferred in on the falling edges of the following clocks. The DAC is updated following the 24th (DAC8411) or 16th (DAC8311) clock cycle, unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC8x11. Refer to the DAC8311 and DAC8411SYNC Interrupt sections for more details.
V_OUT	6	O	Analog output voltage from DAC. The output amplifier has rail-to-rail operation.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Voltage	AV_DD to GND	–0.3	6	V
	Digital input voltage to GND	–0.3	AV_DD +0.3	V
	V_OUT to GND	–0.3	AV_DD +0.3	V
Temperature	Junction, T_J max		150	°C
Temperature	Storage, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±1000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
T_A	Operating temperature	–40		+125	°C
AV_DD	Supply voltage	2.0		+5.5	V

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		DAC8x11	UNIT
		DCK (SC70)
		6 PINS
R_θJA	Junction-to-ambient thermal resistance	216.4	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	52.1	°C/W
R_θJB	Junction-to-board thermal resistance	65.9	°C/W
ψ_JT	Junction-to-top characterization parameter	1.3	°C/W
ψ_JB	Junction-to-board characterization parameter	65.2	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	N/A	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

at AV_DD = 2 V to 5.5 V, R_L = 2 kΩ to GND, and C_L = 200 pF to GND, and T_A = –40°C to +125°C unless otherwise noted.

PARAMETER		TEST CONDITIONS		DAC8411, DAC8311			UNIT
PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
STATIC PERFORMANCE⁽¹⁾
DAC8411	Resolution			16			Bits
	Relative accuracy	Measured by the line passing through codes 485 and 64714	3.6 V to 5 V		±4	±8	LSB
	Relative accuracy	Measured by the line passing through codes 485 and 64714	2 V to 3.6 V		±4	±12	LSB
	Differential nonlinearity				±0.5	±2	LSB
DAC8311	Resolution			14			Bits
	Relative accuracy	Measured by the line passing through codes 120 and 16200			±1	±4	LSB
	Differential nonlinearity				±0.125	±1	LSB
Offset error		Measured by the line passing through two codes⁽²⁾			±0.05	±4	mV
Offset error drift					3		μV/°C
Zero code error		All zeros loaded to the DAC register			0.2		mV
Full-scale error		All ones loaded to DAC register			0.04	0.2	% of FSR
Gain error					0.05	±0.15	% of FSR
Gain temperature coefficient		AV_DD = 5 V			±0.5		ppm of FSR/°C
Gain temperature coefficient		AV_DD = 2 V			±1.5		ppm of FSR/°C
OUTPUT CHARACTERISTICS
Output voltage range				0		AV_DD	V
Output voltage settling time⁽³⁾		R_L = 2 kΩ, C_L = 200 pF, AV_DD = 5 V, 1/4 scale to 3/4 scale			6	10	μs
Output voltage settling time⁽³⁾		R_L = 2 MΩ, C_L = 470 pF			12		μs
Slew rate					0.7		V/μs
Capacitive load stability		R_L = ∞			470		pF
Capacitive load stability		R_L = 2 kΩ			1000		pF
Code change glitch impulse		1LSB change around major carry			0.5		nV-s
Digital feedthrough					0.5		nV-s
Power-on glitch impulse		R_L = 2 kΩ, C_L = 200 pF, AV_DD = 5 V			17		mV
DC output impedance					0.5		Ω
Short-circuit current		AV_DD = 5 V			50		mA
Short-circuit current		AV_DD = 3 V			20		mA
Power-up time		Coming out of power-down mode			50		μs
AC PERFORMANCE
SNR		T_A= 25°C, BW = 20 kHz, 16-bit level, AV_DD = 5 V, f_OUT = 1 kHz, 1st 19 harmonics removed for SNR calculation			88		dB
THD					–66		dB
SFDR					66		dB
SINAD					66		dB
DAC output noise density⁽⁴⁾		T_A= 25°C, at zero-scale input, f_OUT = 1 kHz, AV_DD = 5 V			17		nV/√Hz
DAC output noise density⁽⁴⁾		T_A= 25°C, at mid-code input, f_OUT = 1 kHz, AV_DD = 5 V			110		nV/√Hz
DAC output noise⁽⁵⁾		T_A= 25°C, at mid-code input, 0.1 Hz to 10 Hz, AV_DD = 5 V			3		μV_pp
LOGIC INPUTS⁽³⁾
Input current						±1	μA
V_INL, input low voltage		AV_DD = 2.7 V to 5.5 V				0.3 × AV_DD	V
V_INL, input low voltage		AV_DD = 2 V to 2.7 V				0.1 × AV_DD	V
V_INH, input high voltage		AV_DD = 2.7 V to 5.5 V		0.7 × AV_DD			V
V_INH, input high voltage		AV_DD = 2 V to 2.7 V		0.9 × AV_DD			V
Pin capacitance					1.5	3	pF
POWER REQUIREMENTS
AV_DD				2		5.5	V
I_DD	Normal mode	V_INH = AV_DD and V_INL = GND, at mid-scale code⁽⁶⁾	AV_DD = 3.6 V to 5.5 V		110	160	μA
			AV_DD = 2.7 V to 3.6 V		95	150
			AV_DD = 2 V to 2.7 V		80	140
	All power-down mode	V_INH = AV_DD and V_INL = GND, at mid-scale code⁽⁶⁾	AV_DD = 3.6 V to 5.5 V		0.5	3.5	μA
			AV_DD = 2.7 V to 3.6 V		0.4	3.0
			AV_DD = 2 V to 2.7 V		0.1	2.0
Power dissipation	Normal mode	V_INH = AV_DD and V_INL = GND, at mid-scale code⁽⁶⁾	AV_DD = 3.6 V to 5.5 V		0.55	0.88	mW
			AV_DD = 2.7 V to 3.6 V		0.25	0.54
			AV_DD = 2 V to 2.7 V		0.14	0.38
	All power-down mode	V_INH = AV_DD and V_INL = GND, at mid-scale code⁽⁶⁾	AV_DD = 3.6 V to 5.5 V		2.50	19.2	μW
			AV_DD = 2.7 V to 3.6 V		1.08	10.8
			AV_DD = 2 V to 2.7 V		0.72	8.1

(1) Linearity calculated using a reduced code range of 485 to 64714 for 16-bit, and 120 to 16200 for 14-bit, output unloaded.

(2) Straight line passing through codes 485 and 64714 for 16-bit, and 120 and 16200 for 14-bit, output unloaded.

(3) Specified by design and characterization, not production tested.

(4) For more details, see Figure 33.

(5) For more details, see Figure 34.

(6) For more details, see Figure 14 and Figure 55.

7.6 Timing Requirements: 14-Bit

All specifications at –40°C to 125°C, and AV_DD = 2 V to 5.5 V, unless otherwise noted.⁽¹⁾⁽²⁾

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
f_(SCLK)	Serial clock frequency	AV_DD = 2.0 V to 3.6 V		20	MHz
f_(SCLK)	Serial clock frequency	AV_DD = 3.6 V to 5.5 V		50	MHz
t₁	SCLK cycle time	AV_DD = 2 V to 3.6 V	50		ns
t₁	SCLK cycle time	AV_DD = 3.6 V to 5.5 V	20		ns
t₂	SCLK high time	AV_DD = 2 V to 3.6 V	25		ns
t₂	SCLK high time	AV_DD = 3.6 V to 5.5 V	10		ns
t₃	SCLK low time	AV_DD = 2 V to 3.6 V	25		ns
t₃	SCLK low time	AV_DD = 3.6 V to 5.5 V	10		ns
t₄	SYNC to SCLK rising edge setup time	AV_DD = 2 V to 3.6 V	0		ns
t₄	SYNC to SCLK rising edge setup time	AV_DD = 3.6 V to 5.5 V	0		ns
t₅	Data setup time	AV_DD = 2 V to 3.6 V	5		ns
t₅	Data setup time	AV_DD = 3.6 V to 5.5 V	5		ns
t₆	Data hold time	AV_DD = 2 V to 3.6 V	4.5		ns
t₆	Data hold time	AV_DD = 3.6 V to 5.5 V	4.5		ns
t₇	SCLK falling edge to SYNC rising edge	AV_DD = 2 V to 3.6 V	0		ns
t₇	SCLK falling edge to SYNC rising edge	AV_DD = 3.6 V to 5.5 V	0		ns
t₈	Minimum SYNC high time	AV_DD = 2 V to 3.6 V	50		ns
t₈	Minimum SYNC high time	AV_DD = 3.6 V to 5.5 V	20		ns
t₉	16th SCLK falling edge to SYNC falling edge	AV_DD = 2 V to 3.6 V	100		ns
t₉	16th SCLK falling edge to SYNC falling edge	AV_DD = 3.6 V to 5.5 V	100		ns
t₁₀	SYNC rising edge to 16th SCLK falling edge (for successful SYNC interrupt)	AV_DD = 2 V to 3.6 V	15		ns
t₁₀		AV_DD = 3.6 V to 5.5 V	15		ns

(1) All input signals are specified with t_R = t_F = 3 ns (10% to 90% of AV_DD) and timed from a voltage level of (V_IL + V_IH)/2.

(2) See Figure 1 timing diagram.

7.7 Timing Requirements: 16-Bit

All specifications at –40°C to 125°C, and AV_DD = 2 V to 5.5 V, unless otherwise noted.⁽¹⁾⁽²⁾

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
f(SCLK)	Serial clock frequency	AV_DD = 2.0 V to 3.6 V		20	MHz
f(SCLK)	Serial clock frequency	AV_DD = 3.6 V to 5.5 V		50	MHz
t₁	SCLK cycle time	AV_DD = 2 V to 3.6 V	50		ns
t₁	SCLK cycle time	AV_DD = 3.6 V to 5.5 V	20		ns
t₂	SCLK high time	AV_DD = 2 V to 3.6 V	25		ns
t₂	SCLK high time	AV_DD = 3.6 V to 5.5 V	10		ns
t₃	SCLK low time	AV_DD = 2 V to 3.6 V	25		ns
t₃	SCLK low time	AV_DD = 3.6 V to 5.5 V	10		ns
t₄	SYNC to SCLK rising edge setup time	AV_DD = 2 V to 3.6 V	0		ns
t₄	SYNC to SCLK rising edge setup time	AV_DD = 3.6 V to 5.5 V	0		ns
t₅	Data setup time	AV_DD = 2 V to 3.6 V	5		ns
t₅	Data setup time	AV_DD = 3.6 V to 5.5 V	5		ns
t₆	Data hold time	AV_DD = 2 V to 3.6 V	4.5		ns
t₆	Data hold time	AV_DD = 3.6 V to 5.5 V	4.5		ns
t₇	SCLK falling edge to SYNC rising edge	AV_DD = 2 V to 3.6 V	0		ns
t₇	SCLK falling edge to SYNC rising edge	AV_DD = 3.6 V to 5.5 V	0		ns
t₈	Minimum SYNC high time	AV_DD = 2 V to 3.6 V	50		ns
t₈	Minimum SYNC high time	AV_DD = 3.6 V to 5.5 V	20		ns
t₉	24th SCLK falling edge to SYNC falling edge	AV_DD = 2 V to 3.6 V	100		ns
t₉	24th SCLK falling edge to SYNC falling edge	AV_DD = 3.6 V to 5.5 V	100		ns
t₁₀	SYNC rising edge to 24th SCLK falling edge (for successful SYNC interrupt)	AV_DD = 2 V to 3.6 V	15		ns
t₁₀		AV_DD = 3.6 V to 5.5 V	15		ns

(1) All input signals are specified with t_R = t_F = 3 ns (10% to 90% of AV_DD) and timed from a voltage level of (V_IL + V_IH)/2.

(2) See Figure 2 timing diagram.

DAC8311 DAC8411 tim_ser_14-bit_bas439.gif

Figure 1. Serial Write Operation: 14-Bit (DAC8311)

DAC8311 DAC8411 tim_ser_16-bit_bas439.gif

Figure 2. Serial Write Operation: 16-Bit (DAC8411)

7.8 Typical Characteristics

7.8.1 Typical Characteristics: AV_DD = 5 V

at T_A = 25°C, AV_DD = 5 V, and DAC loaded with mid-scale code, unless otherwise noted.

Figure 3. DAC8411 16-Bit Linearity Error and Differential Linearity Error vs Code (–40°C)

Figure 5. DAC8411 16-Bit Linearity Error and Differential Linearity Error vs Code (25°C)

Figure 7. DAC8411 16-Bit Linearity Error and Differential Linearity Error vs Code (125°C)

DAC8311 DAC8411 tc_zc_error-tmp_5v_bas439.gif

Figure 9. Zero-Code Error vs Temperature

DAC8311 DAC8411 tc_offset-tmp_5v_bas439.gif

Figure 11. Offset Error vs Temperature

DAC8311 DAC8411 tc_fs_error-tmp_5v_bas439.gif

Figure 13. Full-Scale Error vs Temperature

DAC8311 DAC8411 tc_idd-tmp_5v_bas439.gif

Figure 15. Power-Supply Current vs Temperature

DAC8311 DAC8411 tc_is-logic_55v_bas439.gif

Figure 17. Power-Supply Current vs Logic Input Voltage

DAC8311 DAC8411 tc_thd_frq_5v_bas439.gif

Figure 19. Total Harmonic Distortion vs Output Frequency

DAC8311 DAC8411 tc_pwr_density_5v_bas439.gif

Figure 21. Power Spectral Density

DAC8311 DAC8411 tc_gltch_5v_16_ris_bas439.gif

Figure 23. Glitch Energy 5 V, 16-Bit, 1LSB Step, Rising Edge

DAC8311 DAC8411 tc_gltch_5v_14_ris_bas439.gif

Figure 25. Glitch Energy 5 V, 14-Bit, 1LSB Step, Rising Edge

Figure 27. Full-Scale Settling Time 5-V Rising Edge

Figure 29. Half-Scale Settling Time 5-V Rising Edge

DAC8311 DAC8411 tc_gltch_pwron_5v_bas439.gif

Figure 31. Power-On Reset to 0 V Power-On Glitch

DAC8311 DAC8411 tc_noise-frq_5v_bas439.gif

Figure 33. DAC Output Noise Density vs Frequency

Figure 35. Power-Supply Current vs Power-Supply Voltage

DAC8311 DAC8411 tc_le_5v_14bit_40_bas439.gif

Figure 4. DAC8311 14-Bit Linearity Error and Differential Linearity Error vs Code (–40°C)

DAC8311 DAC8411 tc_le_5v_14bit_25_bas439.gif

Figure 6. DAC8311 14-Bit Linearity Error and Differential Linearity Error vs Code (25°C)

DAC8311 DAC8411 tc_le_5v_14bit_125_bas439.gif

Figure 8. DAC8311 14-Bit Linearity Error and Differential Linearity Error vs Code (125°C)

DAC8311 DAC8411 tc_source_pos_5v_bas439.gif

Figure 10. Source Current at Positive Rail

DAC8311 DAC8411 tc_sink_neg_5v_bas439.gif

Figure 12. Sink Current at Negative Rail

DAC8311 DAC8411 tc_idd-code_55v_bas439.gif

Figure 14. Power-Supply Current vs Digital Input Code

DAC8311 DAC8411 tc_ipd-tmp_5v_bas439.gif

Figure 16. Power-Down Current vs Temperature

Figure 18. Power-Supply Current Histogram

DAC8311 DAC8411 tc_snr_frq_5v_bas439.gif

Figure 20. Signal-to-Noise Ratio vs Output Frequency

DAC8311 DAC8411 tc_clk_fdthru_5v_bas439.gif

Figure 22. Clock Feedthrough 5 V, 2 mHz, Midscale

DAC8311 DAC8411 tc_gltch_5v_16_fal_bas439.gif

Figure 24. Glitch Energy 5 V, 16-Bit, 1LSB Step, Falling Edge

DAC8311 DAC8411 tc_gltch_5v_14_fal_bas439.gif

Figure 26. Glitch Energy 5 V, 14-Bit, 1LSB Step, Falling Edge

Figure 28. Full-Scale Settling Time 5-V Falling Edge

Figure 30. Half-Scale Settling Time 5-V Falling Edge

DAC8311 DAC8411 tc_gltch_pwroff_5v_bas439.gif

Figure 32. Power-Off Glitch

DAC8311 DAC8411 tc_dac_noise_5v_bas439.gif

Figure 34. DAC Output Noise 0.1 Hz to 10 Hz Bandwidth

Figure 36. Power-Down Current vs Power-Supply Voltage

7.8.2 Typical Characteristics: AV_DD = 3.6 V

at T_A = 25°C, and AV_DD = 3.6 V, unless otherwise noted.

DAC8311 DAC8411 tc_idd-code_36v_bas439.gif

Figure 37. Power-Supply Current vs Digital Input Code

DAC8311 DAC8411 tc_is-logic_36v_bas439.gif

Figure 39. Power-Supply Current vs Logic Input Voltage

DAC8311 DAC8411 tc_source_pos_36v_bas439.gif

Figure 41. Source Current at Positive Rail

Figure 43. Power-Supply Current Histogram

DAC8311 DAC8411 tc_idd-tmp_36v_bas439.gif

Figure 38. Power-Supply Current vs Temperature

DAC8311 DAC8411 tc_ipd-tmp_36v_bas439.gif

Figure 40. Power-Down Current vs Temperature

DAC8311 DAC8411 tc_sink_neg_36v_bas439.gif

Figure 42. Sink Current at Negative Rail

7.8.3 Typical Characteristics: AV_DD = 2.7 V

at T_A = 25°C, and AV_DD = 2.7 V, unless otherwise noted.

Figure 44. DAC8411 16-Bit Linearity Error and Differential Linearity Error vs Code (–40°C)

Figure 46. DAC8411 16-Bit Linearity Error and Differential Linearity Error vs Code (25°C)

DAC8311 DAC8411 tc_le_27v_125_bas439.gif

Figure 48. DAC8411 16-Bit Linearity Error and Differential Linearity Error vs Code (125°C)

DAC8311 DAC8411 tc_zc_error-tmp_27v_bas439.gif

Figure 50. Zero-Code Error vs Temperature

DAC8311 DAC8411 tc_offset-tmp_27v_bas439.gif

Figure 52. Offset Error vs Temperature

DAC8311 DAC8411 tc_fs_error-tmp_27v_bas439.gif

Figure 54. Full-Scale Error vs Temperature

DAC8311 DAC8411 tc_idd-tmp_27v_bas439.gif

Figure 56. Power-Supply Current vs Temperature

DAC8311 DAC8411 tc_is-logic_27v_bas439.gif

Figure 58. Power-Supply Current vs Logic Input Voltage

DAC8311 DAC8411 tc_thd_frq_27v_bas439.gif

Figure 60. Total Harmonic Distortion vs Output Frequency

DAC8311 DAC8411 tc_pwr_density_27v_bas439.gif

Figure 62. Power Spectral Density

DAC8311 DAC8411 tc_gltch_27v_16_ris_bas439.gif

Figure 64. Glitch Energy 2.7 V, 16-Bit, 1LSB Step, Rising Edge

DAC8311 DAC8411 tc_gltch_27v_14_ris_bas439.gif

Figure 66. Glitch Energy 2.7 V, 14-Bit, 1LSB Step, Rising Edge

DAC8311 DAC8411 tc_fs_27v_ris_bas439.gif

Figure 68. Full-Scale Settling Time 2.7 V Rising Edge

DAC8311 DAC8411 tc_hs_27v_ris_bas439.gif

Figure 70. Half-Scale Settling Time 2.7 V Rising Edge

DAC8311 DAC8411 tc_gltch_pwron_27v_bas439.gif

Figure 72. Power-On Reset to 0-V Power-On Glitch

DAC8311 DAC8411 tc_le_27v_14bit_40_bas439.gif

Figure 45. DAC8311 14-Bit Linearity Error and Differential Linearity Error vs Code (–40°C)

DAC8311 DAC8411 tc_le_27v_14bit_25_bas439.gif

Figure 47. DAC8311 14-Bit Linearity Error and Differential Linearity Error vs Code (25°C)

DAC8311 DAC8411 tc_le_27v_14bit_125_bas439.gif

Figure 49. DAC8311 14-Bit Linearity Error and Differential Linearity Error vs Code (125°C)

DAC8311 DAC8411 tc_source_pos_27v_bas439.gif

Figure 51. Source Current at Positive Rail

DAC8311 DAC8411 tc_sink_neg_27v_bas439.gif

Figure 53. Sink Current at Negative Rail

DAC8311 DAC8411 tc_idd-code_27v_bas439.gif

Figure 55. Power-Supply Current vs Digital Input Code

DAC8311 DAC8411 tc_ipd-tmp_27v_bas439.gif

Figure 57. Power-Down Current vs Temperature

Figure 59. Power-Supply Current Histogram

DAC8311 DAC8411 tc_snr_frq_27v_bas439.gif

Figure 61. Signal-to-Noise Ratio vs Output Frequency

DAC8311 DAC8411 tc_clk_fdthru_27v_bas439.gif

Figure 63. Clock Feedthrough 2.7 V, 20 mHz, Midscale

DAC8311 DAC8411 tc_gltch_27v_16_fal_bas439.gif

Figure 65. Glitch Energy 2.7 V, 16-Bit, 1LSB Step, Falling Edge

DAC8311 DAC8411 tc_gltch_27v_14_fal_bas439.gif

Figure 67. Glitch Energy 2.7 V, 14-Bit, 1LSB Step, Falling Edge

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Figure 69. Full-Scale Settling Time 2.7 V Falling Edge

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Figure 71. Half-Scale Settling Time 2.7 V Falling Edge

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Figure 73. Power-Off Glitch