ADS8555 16-Bit, Six-Channel, Simultaneous Sampling Analog-to-Digital Converter

7.3.1.1 Analog Inputs

The inputs and the converters are of the single-ended, bipolar type. The absolute voltage range can be selected using the RANGE pin (in hardware mode) or RANGE_x bits (in software mode) in the control register (CR, see Table 5) to either ±4 V_REF or ±2 V_REF. With the reference set to 2.5 V (CR bit C18 = 0), the input voltage range can be ±10 V or ±5 V. With the reference source set to 3 V (CR bit C18 = 1), an input voltage range of ±12 V or ±6 V can be configured. The logic state of the RANGE pin is latched with the falling edge of BUSY (if CR bit C20 = 0).

The input current on the analog inputs depends on the actual sample rate, input voltage, and signal source impedance. Essentially, the current into the analog inputs charges the internal capacitor array only during the sampling period (t_ACQ). The source of the analog input voltage must be able to charge the input capacitance of 10 pF in ±4-V_REF mode or 20 pF in ±2-V_REF mode to a 12-, 14-, 16-bit accuracy level within the acquisition time of 280 ns at maximum data rate, as shown in Figure 29.

Figure 29. Equivalent Input Circuits

During the conversion period, there is no further input current flow and the input impedance is greater than 1 MΩ. To ensure a defined start condition, the sampling capacitors of the ADS8555 device are precharged to a fixed internal voltage, before switching into sampling mode.

To maintain the linearity of the converter, the inputs must always remain within the specified range of HVSS – 0.2 V to HVDD + 0.2 V.

The minimum –3-dB bandwidth of the driving operational amplifier can be calculated using Equation 1:

Equation 1.

where

• n = 16 (n is the resolution of the device)

With a minimum acquisition time of t_ACQ = 280 ns, the required minimum bandwidth of the driving amplifier is 6.7 MHz. The required bandwidth can be lower if the application allows a longer acquisition time. A gain error occurs if a given application does not fulfill the bandwidth requirement shown in Equation 1.

A driving operational amplifier may not be required if the impedance of the signal source (R_SOURCE) fulfills the requirement of Equation 2:

Equation 2.

where

• n = 16 (n is the resolution of the ADC)
• C_S = 10 pF is the sample capacitor value for V_IN = ±4 × V_REF mode
• R_SER = 200 Ω is the input resistor value
• R_SW = 130 Ω is the switch resistance value

With t_ACQ = 280 ns, the maximum source impedance must be less than 2 kΩ in V_IN = ±4-V_REF mode or less than 0.9 kΩ in V_IN = ±2-V_REF mode. The source impedance can be higher if the application allows longer acquisition time.

7.3.1.2 Analog-to-Digital Converter (ADC)

The devices include six ADCs that operate with either an internal or an external conversion clock. The conversion time is 1.26 μs with the internal conversion clock. When an external clock and reference are used, the minimum conversion time is 925 ns.

7.3.1.3 Conversion Clock

The device uses either an internally-generated or an external (XCLK) conversion clock signal (in software mode only). In default mode, the device generates an internal clock. When the CLKSEL bit is set high (bit C11 in Table 5), an external conversion clock of up to 20 MHz (maximum) can be applied on pin 27. In both cases, 18.5 clock cycles are required for a complete conversion including the precharging of the sample capacitors. The external clock can remain low between conversions.

The conversion clock duty cycle must be 50%. However, the ADS8555 device functions properly with a duty cycle from 45% to 55%.

7.3.1.4 CONVST_x

The analog inputs of each channel pair (CH_x0, CH_x1) are held with the rising edge of the corresponding CONVST_x signal. Only in software mode (except sequential mode), CONVST_A is used for all six ADCs. The conversion automatically starts with the next edge of the conversion clock.

A conversion start must not be issued during an ongoing conversion on the same channel pair. However, conversions are allowed to be initiated on other input pairs; see the Sequential Mode section for more details.

If a parallel interface is used, the behavior of the output port depends on which CONVST_x signals are issued. Figure 30 shows examples of different scenarios.

NOTE:

Boxed areas indicate the minimum required frame to acquire all data.

Figure 30. Data Output vs CONVST_x

7.3.1.5 BUSY/INT

The BUSY signal indicates if a conversion is in progress. The BUSY signal goes high with a rising edge of any CONVST_x signal and goes low when the output data of the last channel pair are available in the respective output register. The readout of the data can be initiated immediately after the falling edge of BUSY.

In sequential mode, the BUSY signal goes low only for one clock cycle; see the Sequential Mode section for more details.

The INT output goes high at completion of a conversion process and remains high after first read data access.

The polarity of the BUSY/INT signal can be changed using Table 5 bit C20.

7.3.1.6 Reference

The ADS8555 device provides an internal, low-drift, 2.5-V reference source. To increase the input voltage range, the reference voltage can be switched to 3-V mode using the VREF bit (bit C18 in the CR). The reference feeds a 10-bit string-DAC controlled by bits C[9:0] in the control register. The buffered DAC output is connected to the REFIO pin. In this way, the voltage at this pin is programmable in 2.44 mV (2.92 mV in 3-V mode) steps and adjustable to the application needs without additional external components. The actual output voltage can be calculated using Equation 3:

Equation 3.

where

• Range = the chosen maximum reference voltage output range (2.5 V or 3 V)
• Code = the decimal value of the DAC register content

Table 1 lists some examples of internal reference DAC settings with a reference range set to 2.5 V. However, to ensure proper performance, the DAC output voltage should not be programmed below 0.5 V.

Decouple the buffered output of the DAC with a 100-nF capacitor (minimum); for best performance, TI recommends a 470-nF capacitor. If the internal reference is placed into power-down (default), an external reference voltage can drive the REFIO pin.

The voltage at the REFIO pin is buffered with three internal amplifiers, one for each ADC pair. The output of each buffer must be decoupled with a 10-μF capacitor between pin pairs 53 and 54, 55 and 56, and 57 and 58. The 10-μF capacitors are available as ceramic 0805-SMD components and in X5R quality.

The internal reference buffers can be powered down to decrease the power dissipation of the device. In this case, external reference drivers can be connected to REFC_A, REFC_B, and REFC_C pins. With 10-μF decoupling capacitors, the minimum required bandwidth can be calculated using Equation 4.

Equation 4.

With the minimum t_CONV of 1.26 μs, the external reference buffers require a minimum bandwidth of 88 kHz.

7.3.2.1 Device Configuration

Depending on the desired mode of operation, the ADS8555 device can be configured using the external pins or the control register (see Table 5), as shown in Table 2.

7.3.2.2 Parallel Interface

To use the device with the parallel interface, hold the PAR/SER pin low. The maximum achievable data throughput rate using the internal clock is 630 kSPS in this case.

Access to the ADS8555 device is controlled as illustrated in Figure 2 and Figure 3.

The device can either operate with a 16-bit (WORD/BYTE pin set low) or an 8-bit (WORD/BYTE pin set high) parallel interface. If 8-bit operation is used, the HB_EN pin selects if the low-byte (DB7 low) or the high-byte (DB7 high) is available on the data output DB[15:8] first.

7.3.2.3 Serial Interface

The serial interface mode is selected by setting the PAR/SER pin high. In this case, each data transfer starts with the falling edge of the frame synchronization input (FS). The conversion results are presented on the serial data output pins SDO_A, SDO_B, and SDO_C depending on the selections made using the SEL_x pins. Starting with the most significant bit (MSB), the output data are changed at the rising edge of SCLK, so that the host processor can read it at the following falling edge.

Serial data input SDI are latched at the falling edge of SCLK.

The serial interface can be used with one, two, or three output ports. These ports are enabled with pins SEL_A, SEL_B, and SEL_C. If all three serial data output ports (SDO_A, SDO_B, and SDO_C) are selected, the data can be read with either two 16-bit data transfers or with one 32-bit data transfer. The data of channels CH_x0 are available first, followed by data from channels CH_x1. The maximum achievable data throughput rate is 450 kSPS in this case.

If the application allows a data transfer using two ports only, SDO_A and SDO_B outputs are used. The device outputs data from channel CH_A0 followed by CH_A1 and CH_C0 on SDO_A, and data from channel CH_B0 followed by CH_B1 and CH_C1 occurs on SDO_B. In this case, a data transfer of three consecutive 16-bit words or one continuous 48-bit word is supported. The maximum achievable data throughput rate is 375 kSPS.

The output SDO_A is selected if only one serial data port is used in the application. The data are available in the following order: CH_A0, CH_A1, CH_B0, CH_B1, CH_C0, and, finally CH_C1. Data can be read using six 16-bit transfers, three 32-bit transfers, or a single 96-bit transfer. The maximum achievable data throughput rate is 250 kSPS in this case.

Figure 1 (the serial operation timing diagram) and Figure 31 illustrate all possible scenarios in more detail.

Figure 31. Serial Interface: Data Output With One or Two Active SDOs

7.3.2.4 Output Data Format

The data output format of the ADS8555 is binary twos complement, as shown in Table 3.

Table 4. Maximum Analog Current (I_AVDD) Demand of the ADS8555

Table 5. Control Register (CR) Map

8.2.1.1 Design Requirements

To begin the design process, a few parameters must be decided upon. The designer must know the following:

• Output range of the potential transformers (elements labeled PT1, PT2, and PT3 in Figure 36)
• Output range of the current transformers (elements labeled CT1, CT2, and CT3 in Figure 36)
• Input impedance required from the analog front end for each channel
• Fundamental frequency of the power system
• Number of harmonics that must be acquired
• Type of signal conditioning required from the analog front end for each channel

8.2.1.2 Detailed Design Procedure

Figure 37 shows the topology chosen to meet the design requirements. A feedback capacitor C_F is included to provide a low-pass filter characteristic and attenuate signals outside the band of interest.

Figure 37. Op Amp in an Inverting Configuration

The potential transformers (PTs) and current transformers (CTs) used in the system depicted in Figure 36 provide the six input variables required. These transformers have a ±10-V output range. Although the PTs and CTs provide isolation from the power system, the value of R_IN is selected as 100 kΩ to provide an additional, high-impedance safety element to the input of the ADC. Moreover, selecting a low-frequency gain of –1 V/V (as shown in Equation 5) provides a ±10-V output that can be fed into the ADS8555 device; therefore, the value of R_F is selected as 100 kΩ.

Equation 5.

The primary goal of the acquisition system depicted in Figure 36 is to measure up to 20 harmonics in a 60-Hz power network. Thus, the analog front-end must have sufficient bandwidth to detect signals up to 1260 Hz, as shown in Equation 6.

Equation 6.

Based on the bandwidth found in Equation 6 the ADS8555 device is set to simultaneously sample all six channels at 15.36 kSPS, which provides enough samples to clearly resolve even the highest harmonic required.

The passband of the configuration shown in Figure 37 is determined by the –3-dB frequency according to Equation 7. The value of C_F is selected as 820 pF, which is a standard capacitance value available in 0603 size (surface-mount component) and such values, combined with that of R_F, result in sufficient bandwidth to accommodate the required 20 harmonics (at 60 Hz).

Equation 7.

The value of R₁ is selected as the parallel combination of R_IN and R_F to prevent the input bias current of the operational amplifier from generating an offset error.

The value of component C₁ is chosen as 0.1 µF to provide a low-impedance path for noise signals that can be picked up by R₁; the 0.1-µF capacitance value improves the EMI robustness and noise performance of the system.

The OPA2277 device is chosen for its low input offset voltage, low drift, bipolar swing, sufficient gain-bandwidth product and low quiescent current. For additional information on the procedure to select SAR ADC input drivers, see reference guide TIDU181.

The charge injection damping circuit is composed of R₂ (49.9 Ω) and C₂ (370 pF); these components reject high-frequency noise and meet the settling requirements of the ADS8555 device input.

Figure 38 shows the reference block used in this design.

Figure 38. Op Amp in an Inverting Configuration

For more information on the design of charge injection damping circuits and reference driving circuits for SAR ADCs, consult reference guide TIDU014.

8.2.1.3 Application Curve

Figure 39 shows the frequency spectrum of the data acquired by the ADS8555 device for a sinusoidal, 20-V_PP input at 60 Hz.

Figure 39. Frequency Spectrum for a Sinusoidal 20-V_PP Signal at 60 Hz

The ac performance parameters are:

• SNR: 91.9 dB
• THD: –99.68 dB
• SNDR: 91.23 dB
• SFDR: 103.65 dB