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  • ADS4229 Dual-Channel, 12-Bit, 250-MSPS Ultralow-Power ADC

    • SBAS550C June   2011  – May 2015 ADS4229

      PRODUCTION DATA.  

  • CONTENTS
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  • ADS4229 Dual-Channel, 12-Bit, 250-MSPS Ultralow-Power ADC
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: ADS4229 (250 MSPS)
    6. 7.6  Electrical Characteristics: General
    7. 7.7  Digital Characteristics
    8. 7.8  LVDS and CMOS Modes Timing Requirements
    9. 7.9  LVDS Timings at Lower Sampling Frequencies
    10. 7.10 CMOS Timings at Lower Sampling Frequencies
    11. 7.11 Serial Interface Timing Characteristics
    12. 7.12 Reset Timing (Only when Serial Interface is Used)
    13. 7.13 Typical Characteristics
      1. 7.13.1 Typical Characteristics: ADS4229
      2. 7.13.2 Typical Characteristics: Contour
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital Functions
      2. 8.3.2 Gain for SFDR/SNR Trade-off
      3. 8.3.3 Offset Correction
      4. 8.3.4 Power-Down
        1. 8.3.4.1 Global Power-Down
        2. 8.3.4.2 Channel Standby
        3. 8.3.4.3 Input Clock Stop
      5. 8.3.5 Output Data Format
    4. 8.4 Device Functional Modes
      1. 8.4.1 Output Interface Modes
        1. 8.4.1.1 Output Interface
        2. 8.4.1.2 DDR LVDS Outputs
        3. 8.4.1.3 LVDS Buffer
        4. 8.4.1.4 Parallel CMOS Interface
        5. 8.4.1.5 CMOS Interface Power Dissipation
        6. 8.4.1.6 Multiplexed Mode of Operation
    5. 8.5 Programming
      1. 8.5.1 Device Configuration
      2. 8.5.2 Parallel Configuration Only
      3. 8.5.3 Serial Interface Configuration Only
      4. 8.5.4 Using Both Serial Interface and Parallel Controls
      5. 8.5.5 Parallel Configuration Details
      6. 8.5.6 Serial Interface Details
        1. 8.5.6.1 Register Initialization
        2. 8.5.6.2 Serial Register Readout
    6. 8.6 Register Maps
      1. 8.6.1 Serial Register Map
      2. 8.6.2 Description of Serial Registers
        1. 8.6.2.1  Register Address 00h (Default = 00h)
        2. 8.6.2.2  Register Address 01h (Default = 00h)
        3. 8.6.2.3  Register Address 03h (Default = 00h)
        4. 8.6.2.4  Register Address 25h (Default = 00h)
        5. 8.6.2.5  Register Address 29h (Default = 00h)
        6. 8.6.2.6  Register Address 2Bh (Default = 00h)
        7. 8.6.2.7  Register Address 3Dh (Default = 00h)
        8. 8.6.2.8  Register Address 3Fh (Default = 00h)
        9. 8.6.2.9  Register Address 40h (Default = 00h)
        10. 8.6.2.10 Register Address 41h (Default = 00h)
        11. 8.6.2.11 Register Address 42h (Default = 00h)
        12. 8.6.2.12 Register Address 45h (Default = 00h)
        13. 8.6.2.13 Register Address 4Ah (Default = 00h)
        14. 8.6.2.14 Register Address 58h (Default = 00h)
        15. 8.6.2.15 Register Address BFh (Default = 00h)
        16. 8.6.2.16 Register Address C1h (Default = 00h)
        17. 8.6.2.17 Register Address CFh (Default = 00h)
        18. 8.6.2.18 Register Address EFh (Default = 00h)
        19. 8.6.2.19 Register Address F1h (Default = 00h)
        20. 8.6.2.20 Register Address F2h (Default = 00h)
        21. 8.6.2.21 Register Address 2h (Default = 00h)
        22. 8.6.2.22 Register Address D5h (Default = 00h)
        23. 8.6.2.23 Register Address D7h (Default = 00h)
        24. 8.6.2.24 Register Address DBh (Default = 00h)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Theory of Operation
      2. 9.1.2 Analog Input
        1. 9.1.2.1 Drive Circuit Requirements
        2. 9.1.2.2 Driving Circuit
      3. 9.1.3 Clock Input
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Analog Input
        2. 9.2.2.2 Common Mode Voltage Output (VCM)
        3. 9.2.2.3 Clock Driver
        4. 9.2.2.4 Digital Interface
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Sharing DRVDD and AVDD Supplies
    2. 10.2 Using DC/DC Power Supplies
    3. 10.3 Power Supply Bypassing
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Grounding
      2. 11.1.2 Exposed Pad
      3. 11.1.3 Routing Analog Inputs
      4. 11.1.4 Routing Digital Outputs
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Definition of Specifications
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE
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DATA SHEET

ADS4229 Dual-Channel, 12-Bit, 250-MSPS Ultralow-Power ADC

1 Features

  • Maximum Sample Rate: 250 MSPS
  • Ultralow Power with Single 1.8-V Supply:
    • 545-mW Total Power at 250 MSPS
  • High Dynamic Performance:
    • 80.8-dBc SFDR at 170 MHz
    • 69.4-dBFS SNR at 170 MHz
  • Crosstalk: > 90 dB at 185 MHz
  • Programmable Gain Up to 6 dB for
    SNR and SFDR Trade-off
  • DC Offset Correction
  • Output Interface Options:
    • 1.8-V Parallel CMOS Interface
    • DDR LVDS With Programmable Swing:
      • Standard Swing: 350 mV
      • Low Swing: 200 mV
  • Supports Low Input Clock Amplitude
    Down to 200 mVPP
  • Package: 9-mm × 9-mm, 64-Pin Quad Flat
    No-Lead (QFN) Package

2 Applications

  • Wireless Communications Infrastructure
  • Software Defined Radio
  • Power Amplifier Linearization

3 Description

The ADS4229 is a member of the ADS42xx ultralow-power family of dual-channel, 12-bit and 14-bit analog-to-digital converters (ADCs). Innovative design techniques are used to achieve high dynamic performance, while consuming extremely low power with a 1.8-V supply. This topology makes the ADS4229 well-suited for multi-carrier, wide-bandwidth communications applications.

The ADS4229 has gain options that can be used to improve spurious-free dynamic range (SFDR) performance at lower full-scale input ranges. This device also includes a dc offset correction loop that can be used to cancel the ADC offset. Both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel complementary metal oxide semiconductor (CMOS) digital output interfaces are available in a compact QFN-64 PowerPAD™ package.

The device includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The ADS4229 is specified over the industrial temperature range (–40°C to +85°C).

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
ADS4229 VQFN (64) 9.00 mm × 9.00 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

ADS4229 Block Diagram

ADS4229 frontpage1_bas550.gif

4 Revision History

Changes from B Revision (August 2012) to C Revision

  • Added Pin Configuration and Functions section, ESD Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

Changes from A Revision (October 2011) to B Revision

  • Changed first sub-bullet of High Dynamic Performance Features bulletGo
  • Changed footnote 1 in CMOS Timings at Lower Sampling FrequenciesGo
  • Changed row D5 and consolidated the two DB rows in Table 10Go
  • Changed Register Address D5hGo
  • Changed title of Register Address DBh, consolidated two DBh registers into oneGo

Changes from * Revision (June 2011) to A Revision

  • Changed ADS4229 Input Common-Mode Voltage parameter in Table 1Go
  • Changed AC power-supply rejection ratio parameter test condition in ADS4229 Electrical Characteristics tableGo
  • Updated Figure 3Go
  • Updated Figure 25Go
  • Updated Figure 31Go
  • Updated Figure 32Go
  • Changed Time Constant, TCCLK × 1/fS (ms) column and footnote 1 in Table 3Go
  • Changed Revised Channel Standby sectionGo
  • Changed High-performance mode parameter description in High-Performance Modes tableGo
  • Changed description of bits[7:2] in Register Address 40hGo
  • Updated Register Address D7h and Register Address D8h tablesGo
  • Updated first paragraph of Analog Input sectionGo
  • Updated first paragraph of Driving Circuit subsectionGo

5 Device Comparison Table

65 MSPS 125 MSPS 160 MSPS 250 MSPS
ADS422x
12-bit family(1)		 ADS4222 ADS4225 ADS4226 ADS4229
ADS424x
14-bit family(1)		 ADS4242 ADS4245 ADS4246 ADS4249
(1) See Table 1 for details on migrating from the ADS62P49 family.

The ADS4229 is pin-compatible with the previous generation ADS62P49 data converter; this similar architecture enables easy migration. However, there are some important differences between the two device generations, summarized in Table 1.

Table 1. Migrating from the ADS62P49

ADS62P49 FAMILY ADS4229
PINS
Pin 22 is NC (not connected) Pin 22 is AVDD
Pins 38 and 58 are DRVDD Pins 38 and 58 are NC (do not connect, must be floated)
Pins 39 and 59 are DRGND Pins 39 and 59 are NC (do not connect, must be floated)
SUPPLY
AVDD is 3.3 V AVDD is 1.9 V
DRVDD is 1.8 V No change
INPUT COMMON-MODE VOLTAGE
VCM is 1.5 V VCM is 0.95 V
SERIAL INTERFACE
Protocol: 8-bit register address and 8-bit register data No change in protocol
New serial register map
EXTERNAL REFERENCE
Supported Not supported

6 Pin Configuration and Functions

RGC Package (LVDS Mode)
64-Pin VQFN
Top View
ADS4229 po_lvds_422x_bas533.gif
1. The PowerPAD is connected to DRGND.
NOTE: NC = do not connect; must float.
RGC Package (CMOS Mode)
64-Pin VQFN
Top View
ADS4229 po_cmos_422x_bas533.gif

Pin Functions (LVDS Mode)

PIN I/O DESCRIPTION
NAME NO.
AGND 17 I Analog ground
18
21
24
27
28
31
32
AVDD 16 I Analog power supply
22
23
34
CLKM 26 I Differential clock negative input
CLKP 25 I Differential clock positive input
CTRL1 35 I Digital control input pins. Together, they control the various power-down modes.
CTRL2 36 I Digital control input pins. Together, they control the various power-down modes.
CTRL3 37 I Digital control input pins. Together, they control the various power-down modes.
CLKOUTP 57 O Differential output clock, true
CLKOUTM 56 O Differential output clock, complement
DA0M 42 O Channel A differential output data pair, D0 and D1 multiplexed
DA0P 43
DA2M 44 O Channel A differential output data D2 and D3 multiplexed
DA2P 45
DA4M 46 O Channel A differential output data D4 and D5 multiplexed
DA4P 47
DA6M 50 O Channel A differential output data D6 and D7 multiplexed
DA6P 51
DA8M 52 O Channel A differential output data D8 and D9 multiplexed
DA8P 53
DA10M 54 O Channel A differential output data D10 and D11 multiplexed
DA10P 55
DB0M 62 O Channel B differential output data pair, D0 and D1 multiplexed
DB0P 63
DB2M 2 O Channel B differential output data D2 and D3 multiplexed
DB2P 3
DB4M 4 O Channel B differential output data D4 and D5 multiplexed
DB4P 5
DB6M 6 O Channel B differential output data D6 and D7 multiplexed
DB6P 7
DB8M 8 O Channel B differential output data D8 and D9 multiplexed
DB8P 9
DB10M 10 O Channel B differential output data D10 and D11 multiplexed
DB10P 11
DRGND 49 I Output buffer ground
PAD
DRVDD 1 I Output buffer supply
48
INP_A 29 I Differential analog positive input, channel A
INM_A 30 I Differential analog negative input, channel A
INP_B 19 I Differential analog positive input, channel B
INM_B 20 I Differential analog negative input, channel B
NC 38 — Do not connect, must be floated
39
40
41
58
59
60
61
RESET 12 I Serial interface RESET input.
When using the serial interface mode, the internal registers must be initialized through a hardware RESET by applying a high pulse on this pin or by using the software reset option; refer to the Serial Interface Configuration section.
In parallel interface mode, the RESET pin must be permanently tied high. SCLK and SEN are used as parallel control pins in this mode. This pin has an internal 150-kΩ pull-down resistor.
SCLK 13 I This pin functions as a serial interface clock input when RESET is low. It controls the low-speed mode selection when RESET is tied high; see Table 7 for detailed information. This pin has an internal 150-kΩ pull-down resistor.
SDATA 14 I Serial interface data input; this pin has an internal 150-kΩ pull-down resistor.
SDOUT 64 O This pin functions as a serial interface register readout when the READOUT bit is enabled. When READOUT = 0, this pin is put into a high-impedance state.
VCM 23 O This pin outputs the common-mode voltage (0.95 V) that can be used externally to bias the analog input pins

Pin Functions (CMOS Mode)

PIN I/O DESCRIPTION
NAME NO.
AGND 17 I Analog ground
18
21
24
27
28
31
32
AVDD 16 I Analog power supply
22
33
34
CLKM 26 I Differential clock negative input
CLKOUT 57 O CMOS output clock
CLKP 25 I Differential clock positive input
CTRL1 35 I Digital control input pins. Together, they control various power-down modes.
CTRL2 36 I Digital control input pins. Together, they control various power-down modes.
CTRL3 37 I Digital control input pins. Together, they control various power-down modes.
DA0 42 O Channel A ADC output data bits, CMOS levels
DA1 43
DA2 44
DA3 45
DA4 46
DA5 47
DA6 50
DA7 51
DA8 52
DA9 53
DA10 54
DA11 55
DB0 62 O Channel B ADC output data bits, CMOS levels
DB1 63
DB2 2
DB3 3
DB4 4
DB5 5
DB6 6
DB7 7
DB8 8
DB9 9
DB10 10
DB11 11
DRGND 49 I Output buffer ground
PAD
DRVDD 1 I Output buffer supply
48
NC — — Do not connect, must be floated
RESET 12 I Serial interface RESET input.
When using the serial interface mode, the internal registers must be initialized through a hardware RESET by applying a high pulse on this pin or by using the software reset option; refer to the Serial Interface Configuration section.
In parallel interface mode, the RESET pin must be permanently tied high. SDATA and SEN are used as parallel control pins in this mode. This pin has an internal 150-kΩ pull-down resistor.
INM_A 30 I Differential analog negative input, channel A
INP_A 29 I Differential analog positive input, channel A
INM_B 20 I Differential analog negative input, channel B
INP_B 19 I Differential analog positive input, channel B
SCLK 13 I This pin functions as a serial interface clock input when RESET is low. It controls the low-speed mode when RESET is tied high; see Table 7 for detailed information. This pin has an internal 150-kΩ pull-down resistor.
SDATA 14 I Serial interface data input; this pin has an internal 150-kΩ pull-down resistor.
SDOUT 64 O This pin functions as a serial interface register readout when the READOUT bit is enabled. When READOUT = 0, this pin is put into a high-impedance state.
SEN 15 I This pin functions as a serial interface enable input when RESET is low. It controls the output interface and data format selection when RESET is tied high; see Table 8 for detailed information. This pin has an internal 150-kΩ pull-up resistor to AVDD.
VCM 23 O This pin outputs the common-mode voltage (0.95 V) that can be used externally to bias the analog input pins
UNUSED 56 — This pin is not used in the CMOS interface

 
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