Power operational amplifier (op amp) applications are extending into areas where higher precision along with high-voltage supplies (> 50 V), and currents from hundreds of milliamperes to amperes are required. The OPA593 is a recent TI power op amp introduction that is usable with power supplies up to 85 V. It is capable of an output current of 0.25 A from a 4 mm × 4 mm, WSON package. However, even with all the OPA593 offers a new semiconductor test application has been identified where a current level up to 0.5 A is a must have.
This application note describes how two OPA593 op amps can have their outputs parallel connected to provide that 0.5-A output current. It provides a circuit design that successfully meets all DC and AC aspects of the application including the ability to drive a load capacitance of 1 µF with complete stability.
The OPA593 high-voltage, high-current operational amplifier (op amp) is finding design-in opportunities in different test platforms and applications. The 85 V single, ±42.5 V dual-supply capability, 0.25-A maximum output drive current, and accurate current limit set (Iset) make it a good match for semiconductor and other component tester applications. Such applications often require rapid supply voltage and load current changes through the test cycle.
Recently, a new test application surfaced from the field that not only required the OPA593 high output voltage capability, but also high output current up to 0.5 A. This is double the normal 0.25-A output load current capability. A single OPA593 device is not able to provide the higher current level, but a pair of OPA593 amplifiers with their outputs connected in a parallel does. It is often assumed that paralleling op amps is an easy thing to do, but then the performance proves to be less than expected in one way or another. However, by applying careful attention to design details such as current balancing, good performance can be achieved.
Parallel output circuits often appear in the application section of the data sheet for a power op amp. Two commonly-shown configurations include a simple parallel-connected pair of op amps seen in Figure 1-1, and a bit more sophisticated Leader-follower circuit shown in Figure 1-2. Both circuits incorporate output ballast resistors, Rb1 and Rb2 that play an important role in the operation of each circuit. The selection of these circuits is discussed in this document. The Leader-follower circuit is more often applied because it provides accurate voltage output Vo level whereas the output of the simple circuit changes with load.
Directly hard-wiring the outputs of two power op amps is not a good electrical practice. If the outputs of the two op amps are directly connected together uneven current sharing can result. That happens because each of the two op amps tries to force a slightly different Vout voltage which is dependent on their individual Vos level. This current imbalance can lead to uneven power dissipation and uneven device heating.
Even though the resulting Vout differences between the op amps may be small, it is the electrical equivalent of connecting two very low-impedance voltage sources directly across one another. The op amp output impedances (Zcl) are very low, typically millohms due to the high loop gain at which each op amp operates. The Zcl differ between them if each op amp has a different closed-loop gain setting as can be the case with the leader-follower configuration. When there is nearly zero connection resistance between the outputs, the current can be quite high and affect the basic circuit functionality. The added output ballast resistances do much to minimize the current that can flow between the two outputs.
An OPA593 leader-follower parallel output circuit is shown in Figure 1-3. The DC voltage and current levels result from the 5-Vdc input, and a resulting output voltage Vout of +50 V. The load current I4 is 0.45 A. Higher output voltage is obtained by increasing the power supplies, up to 85 V across the V+ and V– pins. The output current is upwards to 0.5 A for the two OPA593 op amps in this configuration.
The power dissipations of the OPA593 op amps and the load must be taken into consideration because of power and thermal limitations as with any electronic component. Each OPA593 dissipates 1.25 W, while the 111-Ω load resistor power is 22.5 W for this specific example. The two OPA593 power dissipations become exceedingly high and they go into thermal shutdown if the delta between the supply voltage and theri output voltage is large and sustained for too long.
Remember that the intended application for the presented circuit involves a fast ATE test sequence where the dwell times are short fractions of a second. The average power dissipation in the fast ATE test sequence is much lower than when operating in a continuous high-power dissipation condition.
The Leader-follower configuration offers the following advantages:
The U1 leader amplifier in Figure 1-3 connected as a non-inverting amplifier has its gain set to +10 V/V. The follower amplifier U2, is a simple unity-gain buffer with a gain of +1 V/V. The two op amps U1 and U2 use individual 3.0-Ω output ballast resistors, designated as Rb1 and Rb2. Though the OPA593 typical room temperature Vos (Ta = 25°C) is ±10 μV, it can increase to an overtemperature maximum of ±350 μV. The potentially higher Vos differences between U1 and U2 across temperature reinforces the need for ballasting to minimize the circulating current flow that can occur between their outputs.
The non-inverting of U1 is driven by a +5-Vdc source in the circuit diagram. Its output voltage when measured on the load side of Rb1 is 10 × 5 V, or 50 V. This occurs because Rb1 is within the feedback loop of U1. The voltage at U1 output adjusts to account for the voltage drop developed across Rb1 as the current through the resistor changes.
The follower amplifier U2 senses the voltage directly at the output of U1, and then the output of U2 follows precisely. If the U1 output voltage rises, the output voltage of U2 also rises and compensates for the voltage drop across Rb2 that occurs in response to an I2 increase. I1 and I2 move in unison each providing one-half the total load current I4, which in this example is 450 mA. The U1 and U2 voltage output moved up to +50.69 V, compensating for the 0.69 V voltage drops across Rb1 and Rb2 for the respective I1 and I2 output currents.
There is a reasonable amount of freedom when selecting the Rb1 and Rb2 ballast resistor (Rbal) values. Here are factors to consider to help establish their resistance:
The complete transfer function for the Leader-follower circuit is surprisingly mathematically involved, but when reduced to a simpler form, Vout is equal to:
Vi = Vin Figure 1-3
Vos1 = Input voltage offset of U1
If Rb1 = Rb2, then
Something that may not be immediately apparent with the Vout equation is that the U2 voltage offset voltage (Vos2), is absent from the transfer function. The full transfer function has two equal, but opposite Vos2 terms that directly cancel each other when Rb1 equals Rb2.
The fact that Vos2 cancels out does not mean that it does not have an effect on the circuit. In fact, any Vos2 present results in the U1 and U2 output currents being imbalanced. The higher the Vos2 voltage offset, the higher the imbalance will be. Since the OPA593 has very low Vos the imbalance due to Vos2 is minimal and not necessarily of concern. However, it might be more of an issue for higher power op amps having Vos on the order of millivolts, or more.
The new component test application in consideration not only has the high 0.5-A output current requirement, but the added need to drive a load capacitance up to 1 µF and remain stable in the process. One microfarad is a high-capacitance load for most op amps to drive, including the OPA593. Compensation is required to assure stability, prevent oscillation, and retain good transient response characteristics.
Since the circuit must be compensated to drive the high-capacitance load it makes sense to have a plan going forward because the Leader-follower circuit has multiple loops; the U1 and U2 local loops, and a third loop that begins at the U1 output, goes to the U2 non-inverting input, and then back through Rb2 and Rb1. Compensation made to any one loop has some effect on the overall AC frequency response of the complete circuit. How to go about effectively compensating the circuit may not be readily evident and difficult to determine.
The approach documented here was to compensate U1 and U2 individually, as if each one independently drives the high-capacitive load. Next, evaluate the overall effectiveness of the stability compensation when they are connected back together. This approach turned out to work well for this OPA593 Leader-follower circuit.
Figure 2-1 shows the same circuit configuration as the Figure 1-3 circuit, but with the additional compensation components included. This circuit has proven completely effective driving a load consisting the 1-µF capacitor in parallel a resistance of 100 Ω to 500 Ω. A load resistance added in parallel with the 1-µF load capacitance serves to draw a DC current similar to an active component under test. Both U1 and U2 compensated as explained and as seen in Figure 2-1 have respective unity-gain bandwidths of approximately 55 kHz and 100 kHz. The OPA593 parallel output amplifier bandwidth is sufficient for the intended component test application.
The easiest place to start from a compensation explanation is with U2 in Figure 2-1. U2 is the same follower and 3.0-Ω series output ballast resistor as in the Figure 1-3 DC circuit. What may not be apparent is that Rb2 is doubling as an “Riso” output load isolation resistor now. Adding Riso is one method of compensating an op amp, increasing its ability to drive a high-capacitive load CL and remain stable doing so. A simplified version of the U2 circuit is illustrated in Figure 2-2 where the output ballast resistor is serving the additional function as Riso.
The Riso compensation method is presented and further explained in the online: TI Precision Labs Series – Amplifiers, Op amp Stability – Capacitive Loads.
When the Riso compensation method is used with a single op amp as seen in Figure 2-2, a voltage divider is created by the Riso resistor and RL impedance to ground that follows it. The voltage at the divider output can be less than what is needed. However, when applied as it is in the Leader-follower circuit in Figure 2-1, the output voltage level is automatically corrected level by circuit configuration.
Compensation of U1 is a bit more involved than what was required for U2. As seen in the Figures, the 3.0-Ω ballast resistor Rb1 is positioned within the feedback loop. It is not possible to move the Rb1 outside the loop without completely undoing the way the Figure 2-1 Leader-follower configuration is designed to function.
When the output of the U1 leader amplifier is directly loaded by a 1-µF load capacitance to ground, the phase margin is highly diminished. A TINA-Spice simulation of the U1 circuit indicates a phase margin less than 0°; therefore, the circuit is unstable. The majority of the phase margin reduction is caused by the addition of 1-μF load capacitance at the output with the addition of a few degrees of reduction caused by the necessary inclusion of Rb1 within the U1 feedback loop interacting with the load capacitance.
A gain and phase plot vs. frequency obtained from the simulation demonstrates the normal –90° phase shift coming from the dominant-pole compensation of the op amp, plus another low-frequency pole breaking at about 3 kHz. That second pole adds an additional –90° of phase shift to the overall –180° phase shift. As a result of these first two poles, the phase margin falls to 0° around 23 kHz. The second pole is attributable to the U1 open-loop output impedance (Zo), the 3.0 Ω Rb1 in series with its Zo, the 1-µF load capacitance, and other impedances in the output circuitry.
The compensation goal for U1 is to keep the loop phase from falling to 0°, and to stay as high as possible above as 0°. Adding a Riso resistor like that used with U2, external to the feedback loop, is not an option here. Another method for compensating U1 is needed.
It was determined that compensating U1 for the phase shift added by the 3-kHz second pole can be accomplished by adding a capacitor across the 4.5-kΩ, feedback resistor on U1. That capacitor, when set to a value of 1.5 nF, introduces a zero into the U1 loop response in the 20- to 30-kHz frequency range. The loop-gain roll-off, which was –40 dB/dec without the capacitor, then bends upward to reduce the roll-off rate to –20 dB/dec. The added zero counters the negative phase shift of the second pole and flattens the phase sufficiently such that the phase margin of U1 remains is about 40° at 56 kHz, where the loop-gain passes through 0 dB.
The compensations applied at U1 and U2 result in phase margins of about 40° and 70°, respectively, when driving the 1-µF, 500-Ω parallel load. Those margins increase as the load resistance of the output load is reduced in value. The margins increase to 69° and 89°, respectively, when the output load is just a 500-Ω resistance.
The OPA593 parallel output amplifier compensated as described and as shown in Figure 2-1 remained stable with a variety of parallel R and C load combinations tested on the bench. The compensation developed for this amplifier has been optimized for that specific load. If the load capacitance is further increased, or even decreased, the phase margin can decrease. Compensation developed for a specific complex load does not necessarily make sure it provides an acceptable high phase margin with a different load.
The final test circuit of Figure 2-1 was realized by connecting two OPA593EVM evaluation modules together. The bench tests were intended to evaluate the OPA593 parallel 0.5-A output current capability, and to observe the output behaviors when loaded with different RL and CL loads. Figure 3-1 shows the two EVMs and the bench test equipment setup ready for testing.
The first test evaluated a sine-wave output of 0 to 50 V, developed across a 100 Ω, 20 W resistive load. This equated to 0.5-A peak output current. The OPA593EVM power supplies were set to +55 V and –5 V, and current-limit Rset resistors were set to 2.29 kΩ to set the maximum output current limit to about 250 mA for each OPA593EVM. Current limiting should then occur within the OPA593 ±5% rated limit is exceeded. The input stimulus was +2.5 Vdc, plus a 5 Vpp 1-kHz sine wave.
In Figure 3-2 the top trace is the +2.5 Vdc, plus a 5 Vpp 1-kHz sine measured at the U1 non-inverting input. The middle trace is the output sine waveform coming from the two OPA593 parallel outputs producing a peak-to-peak output that extends from 0 V to 50 V. The lower trace is a 200 mA/div current measurement acquired using a Tek TCPA300 AC/DC current probe. The trace verifies that a peak 0.5-A current is being produced by the parallel output amplifier when driving the 100-Ω load.
An attempt to drive the circuit harder and produce more output current resulted in one or both of the OPA593 op amps hitting their user-established automatic current limit of approximately 250 mA. The OPA593 EVM current-limit LED turned on when the internal current limit of the op amp was activated. As a consequence, the output sine wave became clipped on the current peaks verifying the current limiting was activated. This current-limit feature provides protection for both the OPA593 and the load it is driving.
The final test conducted was to observe the OPA593 parallel output behavior when driving a 1-µF, 500-Ω parallel load. The compensation was optimized to drive this particular load as mentioned previously.
An indirect method that can be applied to evaluate the phase margin of an op-amp circuit involves a small-signal transient overshoot test (dominant 2-pole system). This test is presented in TI's Analog Engineer’s Pocket Reference Guide in the Amplifier section. The test applies a low-level step, or square-wave to the input of the amplifier. The output step is kept to about 50- to 100-mV peak to avoid slew rate limiting. Then, the overshoot amplitude is measured relative to the settled output amplitude. Figures 46 and 47 in the pocket reference guide show how the phase margin is estimated from a graph.
A phase margin of 45° provides sufficient margin for many applications and also provides stable operation. A phase margin of 45° correlates with an overshoot of approximately 25% as shown in the graph in Figure 47 of the pocket reference guide. A compensated op amp driving a highly reactive load such as the parallel 500-Ω, 1-µF load, can have even less phase margin because of the very high C-load. Strive to compensate it for a minimum phase margin of no less than 30°. Transient behaviors degrade with low phase margin resulting in high overshoot and long settling times. Their degradation can become an issue that places limits on the dynamic performance of a system.
Figure 3-3 shows the small-signal transient response obtained from the OPA593 parallel output amplifier when driving the 1-µF, 500-Ω parallel load. The blue output voltage and pink output current traces exhibit only a small amount of overshoot and fast settling. This result supports a phase margin that is closer to 50° to 60°. That is, the margin is higher than the simulation results that produced approximately 40° for U1, and lower than 70° for U2. The OPA593 model provides a close approximation of the electrical performances of the amplifier and comes close to the correct answer. However, the bench measurement provides a more thorough system evaluation that uses the actual OPA593 op amps.
Tests conducted with a large signal, square-wave output while driving a high-capacitive load of hundreds of nanofarads and 1 µF caused dim lighting of the OPA593EVM current-limit LEDs. The LED response was determined to be the result of the output current attempting to exceed the 250 mA set current limit of each EVM. This occurred during the transition of the output square wave from low level to high level. It was simply a matter of the edge transition current of the square wave, i = C dv/dt. The faster the edge rate, the higher the instantaneous current is for a particular load capacitance. The LED lighting was the result of the current limiting during the dv/dt event period.
A practical design for an OPA593 device in a Leader-follower parallel output configuration was developed and tested with good results. The circuit is applicable to numerous component test and analog power applications. Special attention was made to balancing the output current load shared between the two OPA593 high-voltage, high-current op amps. The circuit readily delivered a 0.5-A output current to a 100 Ω load. Particular attention was paid to compensating the amplifier circuit so that it could readily drive a high-capacitance 1-µF load. The OPA593 parallel output amplifier maintained complete stability for all output loads tested.
Changes from Revision * (August 2022) to Revision A (January 2023)
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