The TPS7A8101 low-dropout linear regulator (LDO) offers very good performance in noise and power-supply rejection ratio (PSRR) at the output. This LDO uses an advanced BiCMOS process and a PMOSFET pass device to achieve very low noise, excellent transient response, and excellent PSRR performance.
The TPS7A8101 device is stable with a 4.7-μF ceramic output capacitor, and uses a precision voltage reference and feedback loop to achieve a worst-case accuracy of 3% over all load, line, process, and temperature variations.
This device is fully specified over the temperature range of TJ = –40°C to 125°C and is offered in a 3-mm × 3-mm, SON-8 package with a thermal pad.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS7A8101 | SON (8) | 3.00 mm × 3.00 mm |
Changes from A Revision (April 2012) to B Revision
Changes from * Revision (December 2011) to A Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
EN | 5 | I | Driving this pin high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. Refer to the Shutdown section for more details. EN must not be left floating and can be connected to IN if not used. |
FB | 3 | I | This pin is the input to the control-loop error amplifier and is used to set the output voltage of the device. |
GND | 4, pad | — | Ground |
IN | 7 | I | Unregulated input supply |
8 | |||
NR | 6 | — | Connect an external capacitor between this pin and ground to reduce output noise to very low levels. The capacitor also slows down the VOUT ramp (RC softstart). |
OUT | 1 | O | Regulator output. A 4.7-μF or larger capacitor of any type is required for stability. |
2 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage | IN | –0.3 | 7 | V |
FB, NR | –0.3 | 3.6 | ||
EN | –0.3 | VIN + 0.3(2) | ||
OUT | –0.3 | 7 | ||
Current | OUT | Internally Limited | A | |
Temperature | Operating virtual junction, TJ | –55 | 150 | °C |
Storage, Tstg | –55 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2000 | V | |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±500 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VI | Input voltage | 2.2 | 6.5 | V |
IO | Output current | 0 | 1 | A |
TA | Operating free air temperature | –40 | 125 | °C |
THERMAL METRIC(1) | TPS7A8101 | UNIT | |
---|---|---|---|
DRV (SON) | |||
8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 47.8 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 53.9 | °C/W |
RθJB | Junction-to-board thermal resistance | 23.4 | °C/W |
ψJT | Junction-to-top characterization parameter | 1 | °C/W |
ψJB | Junction-to-board characterization parameter | 23.5 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 7.4 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
VIN | Input voltage range(1) | 2.2 | 6.5 | V | ||||
VNR | Internal reference | 0.79 | 0.8 | 0.81 | V | |||
VOUT | Output voltage range | 0.8 | 6 | V | ||||
Output accuracy(2) | VOUT + 0.5 V ≤ VIN ≤ 6 V, VIN ≥ 2.5 V, 100 mA ≤ IOUT ≤ 500 mA, 0°C ≤ TJ ≤ 85°C |
-2% | 2% | |||||
VOUT + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.2 V, 100 mA ≤ IOUT ≤ 1 A |
–3% | ±0.3% | 3% | |||||
ΔVO(ΔVI) | Line regulation | VOUT(NOM) + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.2 V, IOUT = 100 mA |
150 | μV/V | ||||
ΔVO(ΔIL) | Load regulation | 100 mA ≤ IOUT ≤ 1 A | 2 | μV/mA | ||||
VDO | Dropout voltage(3) | VOUT + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.2 V, IOUT = 500 mA, VFB = GND or VSNS = GND |
250 | mV | ||||
VOUT + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.5 V, IOUT = 750 mA, VFB = GND or VSNS = GND |
350 | |||||||
VOUT + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.5 V, IOUT = 1 A, VFB = GND or VSNS = GND |
500 | |||||||
ILIM | Output current limit | VOUT = 0.85 × VOUT(NOM), VIN ≥ 3.3 V | 1100 | 1400 | 2000 | mA | ||
IGND | Ground pin current | IOUT = 1 mA | 60 | 100 | μA | |||
IOUT = 1 A | 350 | |||||||
ISHDN | Shutdown current (IGND) | VEN ≤ 0.4 V, VIN ≥ 2.2 V, RL = 1 kΩ, 0°C ≤ TJ ≤ 85°C |
0.2 | 2 | μA | |||
IFB | Feedback pin current | VIN = 6.5 V, VFB = 0.8 V | 0.02 | 1 | μA | |||
PSRR | Power-supply rejection ratio | VIN = 4.3 V, VOUT = 3.3 V, IOUT = 750 mA |
f = 100 Hz | 80 | dB | |||
f = 1 kHz | 82 | |||||||
f = 10 kHz | 78 | |||||||
f = 100 kHz | 60 | |||||||
f = 1 MHz | 54 | |||||||
Vn | Output noise voltage | BW = 100 Hz to 100 kHz, VIN = 3.8 V, VOUT = 3.3 V, IOUT = 100 mA, CNR = CBYPASS = 470 nF |
23.5 | μVRMS | ||||
VEN(HI) | Enable high (enabled) | 2.2 V ≤ VIN ≤ 3.6 V, RL = 1 kΩ | 1.2 | V | ||||
3.6 V < VIN ≤ 6.5 V, RL = 1 kΩ | 1.35 | |||||||
VEN(LO) | Enable low (shutdown) | RL = 1 kΩ | 0 | 0.4 | V | |||
IEN(HI) | Enable pin current, enabled | VIN = VEN = 6.5 V | 0.02 | 1 | μA | |||
tSTR | Start-up time | VOUT(NOM) = 3.3 V, VOUT = 0% to 90% VOUT(NOM), RL = 3.3 kΩ, COUT = 10 μF, CNR = 470 nF |
80 | ms | ||||
UVLO | Undervoltage lockout | VIN rising, RL = 1 kΩ | 1.86 | 2 | 2.10 | V | ||
Hysteresis | VIN falling, RL = 1 kΩ | 75 | mV | |||||
TSD | Thermal shutdown temperature | Shutdown, temperature increasing | 160 | °C | ||||
Reset, temperature decreasing | 140 | °C | ||||||
TJ | Operating junction temperature | –40 | 125 | °C |
NOTE: The Y-axis shows 1% VO per division | ||
VO = 0.8 V | IO = 750 mA | |
NOTE: The Y-axis shows 1% VO per division |
IO = 1 A | ||
IO = 500 mA | ||
VI = 3.6 V | ||
VO = VI – 0.5 V |
VI – VO = 1 V | C(IN) = 0 F | C(OUT) = 10 µF |
C(NR) = C(BYPASS) = 470 nF |
VI – VO = 1 V | C(IN) = 0 F | C(OUT) = 10 µF |
C(NR) = C(BYPASS) = 470 nF |
IO = 100 mA | C(IN) = 0 F |
VI – VO = 0.5 V | C(OUT) = 10 µF | C(IN) = 10 µF | |
24.09 µVRMS (C(NR) = C(BYPASS) = 100 nF) | |||
23.54 µVRMS (C(NR) = C(BYPASS) = 470 nF) |
23.54 µVRMS (IO = 100 mA) | C(IN) = 10 µF | VI – VO = 0.5 V |
23.71 µVRMS (IO = 750 mA) | C(NR) = 470 nF | C(OUT) = 10 µF |
22.78 µVRMS (IO = 1 A) | C(BYPASS) = 470 nF |
Using the same value of C(NR) and C(BYPASS) in the X-Axis |
IO = 100 mA → 1 A → 100 mA | ||
RL = 33 Ω | C(NR) = 470 nF | C(BYPASS) = 470 nF | ||
C(OUT) = 10 µF | C(IN) = 10 µF | |||
(1) The internal reference requires approximately 80 ms of rampup time (see Start-Up) from the enable event; therefore, VO fully reaches the target output voltage of 3.3 V in 80 ms from start-up. |
NOTE: The Y-axis shows 1% VO per division | ||
VO = 0.8 V | IO = 5 mA | |
NOTE: The Y-axis shows 1% VO per division |
IO = 750 mA | ||
VI = 3.6 V | ||
VO = 0.8 V | IO = 750 mA | |
V(EN) = 0.4 V | ||
C(NR) = C(BYPASS) = 470 nF | C(OUT) = 10 µF | C(IN) = 0 F |
VI – VO = 0.5 V | C(IN) = 0 F | C(OUT) = 10 µF |
C(NR) = C(BYPASS) = 470 nF |
VI – VO = 0.5 V | C(IN) = 0 F | C(OUT) = 10 µF |
C(NR) = C(BYPASS) = 470 nF |
IO = 750 mA | C(IN) = 0 F |
25.89 µVRMS (VO = 1.8 V) | C(IN) = 10 µF | VI – VO = 0.5 V |
23.54 µVRMS (VO = 2.5 V) | C(NR) = 470 nF | C(OUT) = 10 µF |
23.54 µVRMS (VO = 3.3 V) | C(BYPASS) = 470 nF |
23.54 µVRMS (CO = 10 µF) | C(IN) = 10 µF | VI – VO = 0.5 V |
23.91 µVRMS (CO = 22 µF) | C(NR) = 470 nF | C(OUT) = 10 µF |
22.78 µVRMS (CO = 100 µF) | C(BYPASS) = 470 nF |
VI = 3.8 V → 4.8 V → 3.8 V | ||
IO = 500 mA |
RL = 33 Ω | C(NR) = 470 nF | C(BYPASS) = 470 nF |
C(OUT) = 10 µF | C(IN) = 10 µF |
The TPS7A8101 device belongs to a family of new-generation LDO regulators that use innovative circuitry to achieve wide bandwidth and high loop gain, resulting in extremely high PSRR (over a 1-MHz range) even with very low headroom (VI – VO). A noise-reduction capacitor (C(NR)) at the NR pin and a bypass capacitor (C(BYPASS)) decrease noise generated by the bandgap reference to improve PSRR, while a quick-start circuit fast-charges the noise-reduction capacitor. This family of regulators offers sub-bandgap output voltages, current limit, and thermal protection, and is fully specified from –40°C to 125°C.
The TPS7A8101 internal current limit helps protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of output voltage. For reliable operation, the device should not be operated in a current limit state for extended periods of time.
The PMOS pass element in the TPS7A8101 has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting may be appropriate.
The enable pin (EN) is active high and is compatible with standard and low voltage, TTL-CMOS levels. When shutdown capability is not required, EN can be connected to IN.
Through a lower resistance, the bandgap reference can quickly charge the noise reduction capacitor (CNR). The TPS7A8101 has a quick-start circuit to quickly charge CNR, if present; see the . At start-up, this quick-start switch is closed, with only 33 kΩ of resistance between the bandgap reference and the NR pin. The quick-start switch opens approximately 100 ms after any device enabling event, and the resistance between the bandgap reference and the NR pin becomes higher in value (approximately 250 kΩ) to form a very good low-pass (RC) filter. This low-pass filter achieves very good noise reduction for the reference voltage.
Inrush current can be a problem in many applications. The 33-kΩ resistance during the start-up period is intentionally put there to slow down the reference voltage ramp up, thus reducing the inrush current. For example, the capacitance of connecting the recommended CNR value of 0.47 μF along with the 33-kΩ resistance causes approximately 80-ms RC delay. Start-up time with the other CNR values can be calculated as:
Although the noise reduction effect is nearly saturated at 0.47 μF, connecting a CNR value greater than 0.47 μF can help reduce noise slightly more; however, start-up time will be extremely long because the quick-start switch opens after approximately 100 ms. That is, if CNR is not fully charged during this 100-ms period, CNR finishes charging through a higher resistance of 250 kΩ, and takes much longer to fully charge.
A low leakage CNR should be used; most ceramic capacitors are suitable.
The TPS7A8101 uses an undervoltage lock-out circuit to keep the output shut off until the internal circuitry is operating properly. The UVLO circuit has a de-glitch feature so that it typically ignores undershoot transients on the input if they are less than 50-μs duration.
Driving the EN pin over 1.2 V for VI from 2.2 V to 3.6 V or 1.35 V for VI from 3.6 V to 6.5 V turns on the regulator. Driving the EN pin below 0.4 V causes the regulator to enter shutdown mode.
In shutdown, the current consumption of the device is reduced to 0.02 µA typically.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The TPS7A8101 belongs to a family of new generation LDO regulators that use innovative circuitry to achieve wide bandwidth and high loop gain, resulting in extremely high PSRR (over a 1-MHz range) at very low headroom (VIN – VOUT). A noise reduction capacitor (CNR) at the NR pin and a bypass capacitor (CBYPASS) bypass noise generated by the bandgap reference to improve PSRR, while a quick-start circuit fast-charges the noise reduction capacitor. This family of regulators offers sub-bandgap output voltages, current limit, and thermal protection, and is fully specified from –40°C to 125°C.
SYMBOL | NAME | VALUE |
---|---|---|
CIN | Input capacitor | 10 µF |
COUT | Output capacitor | 10 µF |
CNR | Noise reduction capacitor between NR and GND | 470 nF |
CBYPASS | Noise reduction capacitor across R1 | 470 nF |
VOUT | R1 | R2 |
---|---|---|
0.8 V | 0 Ω (Short) | 10 kΩ |
1 V | 2.49 kΩ | 10 kΩ |
1.2 V | 4.99 kΩ | 10 kΩ |
1.5 V | 8.87 kΩ | 10 kΩ |
1.8 V | 12.5 kΩ | 10 kΩ |
2.5 V | 21 kΩ | 10 kΩ |
3.3 V | 30.9 kΩ | 10 kΩ |
5 V | 52.3 kΩ | 10 kΩ |
Figure 31 illustrates the connections for the device.
The TPS7A8101 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in its linear region of operation and the input-to-output resistance is the RDS(ON) of the PMOS pass element. VDO scales approximately with output current because the PMOS device in dropout behaves the same way as a resistor.
As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout. This effect is shown in Figure 19 and Figure 20 in the Typical Characteristics section.
The TPS7A8101 is stable and well-behaved with no output load. Traditional PMOS LDO regulators suffer from lower loop gain at very light output loads. The TPS7A8101 employs an innovative low-current mode circuit to increase loop gain under very light or no-load conditions, resulting in improved output voltage regulation performance down to zero output current.
Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to 1-μF low equivalent series resistance (ESR) capacitor across the input supply near the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated or if the device is located several inches from the power source. If source impedance is not sufficiently low, a 0.1-μF input capacitor may be necessary to ensure stability.
The TPS7A8101 is designed to be stable with standard ceramic capacitors of capacitance values 4.7 μF or larger. This device is evaluated using a 10-μF ceramic capacitor of 10-V rating, 10% tolerance, X5R type, and 0805 size (2 mm × 1.25 mm).
X5R- and X7R-type capacitors are highly recommended because they have minimal variation in value and ESR over temperature. Maximum ESR should be less than 1 Ω.
The voltage on the FB pin sets the output voltage and is determined by the values of R1 and R2. The values of R1 and R2 can be calculated for any voltage using the formula given in Equation 2:
Table 2 shows sample resistor values for common output voltages. In Table 2, E96 series resistors are used, and all values meet 1% of the target VOUT, assuming resistors with zero error. For the actual design, pay attention to any resistor error factors. Using lower values for R1 and R2 reduces the noise injected from the FB pin.
In most LDOs, the bandgap is the dominant noise source. If a noise reduction capacitor (CNR) is used with the TPS7A8101, the bandgap does not contribute significantly to noise. Instead, noise is dominated by the output resistor divider and the error amplifier input. If a bypass capacitor (CBYPASS) across the high-side feedback resistor (R1) is used with the TPS7A8101 in addition to CNR, noise from these other sources can also be significantly reduced.
To maximize noise performance in a given application, use a 0.47-μF noise-reduction capacitor plus a 0.47-μF bypass capacitor.
As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude but increases duration of the transient response. Line transient performance can be improved by using a larger noise reduction capacitor (CNR) and/or bypass capacitor (CBYPASS).
The device is designed to operate from an input voltage supply range from 2.2 V to 6.5 V. The input voltage range should provide adequate headroom for the device to have a regulated output. This input supply should be well regulated. If the input supply is noisy, additional input capacitors with low ESR can help improve the output noise performance.
To improve AC performance such as PSRR, output noise, and transient response, TI recommends designing the board with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the GND pin of the device.
Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the device to cool. When the junction temperature cools to approximately 140°C the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage because of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to 125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least 35°C above the maximum expected ambient condition of your particular application. This configuration produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load.
The internal protection circuitry of the TPS7A8101 has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TPS7A8101 into thermal shutdown degrades device reliability.
Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the tab or pad is critical to avoiding thermal shutdown and ensuring reliable operation.
Power dissipation of the device depends on input voltage and load conditions and can be calculated using Equation 3:
Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input voltage necessary to achieve the required output voltage regulation.
On the SON (DRB) package, the primary conduction path for heat is through the exposed pad to the printed-circuit-board (PCB). The pad can be connected to ground or be left floating; however, it should be attached to an appropriate amount of copper PCB area to ensure the device does not overheat. The maximum junction-to-ambient thermal resistance depends on the maximum ambient temperature, maximum device junction temperature, and power dissipation of the device and can be calculated using Equation 4:
Knowing the maximum RθJA, the minimum amount of PCB copper area needed for appropriate heatsinking can be estimated using Figure 34.
NOTE:
θJA value at board size of 9 in2 (that is, 3 in × 3 in) is a JEDEC standard.Figure 34 shows the variation of θJA as a function of ground plane copper area in the board. It is intended only as a guideline to demonstrate the effects of heat spreading in the ground plane and should not be used to estimate actual thermal performance in real application environments.
NOTE
When the device is mounted on an application PCB, it is strongly recommended to use ΨJT and ΨJB, as explained in the section.
Using the thermal metrics ΨJT and ΨJB, as shown in the Thermal Information table, the junction temperature can be estimated with corresponding formulas (given in Equation 5). For backwards compatibility, an older θJC,Top parameter is listed as well.
Where PD is the power dissipation shown by Equation 4, TT is the temperature at the center-top of the IC package, and TB is the PCB temperature measured 1 mm away from the IC package on the PCB surface (as Figure 35 shows).
NOTE
Both TT and TB can be measured on actual application boards using an infrared thermometer.
For more information about measuring TT and TB, see the application note SBVA025, Using New Thermal Metrics, available for download at www.ti.com.
By looking at Figure 36, the new thermal metrics (ΨJT and ΨJB) have very little dependency on board size. That is, using ΨJT or ΨJB with Equation 5 is a good way to estimate TJ by simply measuring TT or TB, regardless of the application board size.
For a more detailed discussion of why TI does not recommend using θJC(top) to determine thermal characteristics, refer to application report SBVA025, Using New Thermal Metrics, available for download at www.ti.com. For further information, refer to application report SPRA953, IC Package Thermal Metrics, also available on the TI website.