The TPS7A8101 low-dropout linear regulator (LDO) offers very good performance in noise and power-supply rejection ratio (PSRR) at the output. This LDO uses an advanced BiCMOS process and a PMOSFET pass device to achieve very low noise, excellent transient response, and excellent PSRR performance.
The TPS7A8101 device is stable with a 4.7-μF ceramic output capacitor, and uses a precision voltage reference and feedback loop to achieve a worst-case accuracy of 3% over all load, line, process, and temperature variations.
This device is fully specified over the temperature range of TJ = –40°C to 125°C and is offered in a 3-mm × 3-mm, SON-8 package with a thermal pad.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS7A8101 | SON (8) | 3.00 mm × 3.00 mm |
Changes from A Revision (April 2012) to B Revision
Changes from * Revision (December 2011) to A Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
EN | 5 | I | Driving this pin high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. Refer to the Shutdown section for more details. EN must not be left floating and can be connected to IN if not used. |
FB | 3 | I | This pin is the input to the control-loop error amplifier and is used to set the output voltage of the device. |
GND | 4, pad | — | Ground |
IN | 7 | I | Unregulated input supply |
8 | |||
NR | 6 | — | Connect an external capacitor between this pin and ground to reduce output noise to very low levels. The capacitor also slows down the VOUT ramp (RC softstart). |
OUT | 1 | O | Regulator output. A 4.7-μF or larger capacitor of any type is required for stability. |
2 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage | IN | –0.3 | 7 | V |
FB, NR | –0.3 | 3.6 | ||
EN | –0.3 | VIN + 0.3(2) | ||
OUT | –0.3 | 7 | ||
Current | OUT | Internally Limited | A | |
Temperature | Operating virtual junction, TJ | –55 | 150 | °C |
Storage, Tstg | –55 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2000 | V | |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±500 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VI | Input voltage | 2.2 | 6.5 | V |
IO | Output current | 0 | 1 | A |
TA | Operating free air temperature | –40 | 125 | °C |
THERMAL METRIC(1) | TPS7A8101 | UNIT | |
---|---|---|---|
DRV (SON) | |||
8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 47.8 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 53.9 | °C/W |
RθJB | Junction-to-board thermal resistance | 23.4 | °C/W |
ψJT | Junction-to-top characterization parameter | 1 | °C/W |
ψJB | Junction-to-board characterization parameter | 23.5 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 7.4 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
VIN | Input voltage range(1) | 2.2 | 6.5 | V | ||||
VNR | Internal reference | 0.79 | 0.8 | 0.81 | V | |||
VOUT | Output voltage range | 0.8 | 6 | V | ||||
Output accuracy(2) | VOUT + 0.5 V ≤ VIN ≤ 6 V, VIN ≥ 2.5 V, 100 mA ≤ IOUT ≤ 500 mA, 0°C ≤ TJ ≤ 85°C |
-2% | 2% | |||||
VOUT + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.2 V, 100 mA ≤ IOUT ≤ 1 A |
–3% | ±0.3% | 3% | |||||
ΔVO(ΔVI) | Line regulation | VOUT(NOM) + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.2 V, IOUT = 100 mA |
150 | μV/V | ||||
ΔVO(ΔIL) | Load regulation | 100 mA ≤ IOUT ≤ 1 A | 2 | μV/mA | ||||
VDO | Dropout voltage(3) | VOUT + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.2 V, IOUT = 500 mA, VFB = GND or VSNS = GND |
250 | mV | ||||
VOUT + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.5 V, IOUT = 750 mA, VFB = GND or VSNS = GND |
350 | |||||||
VOUT + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.5 V, IOUT = 1 A, VFB = GND or VSNS = GND |
500 | |||||||
ILIM | Output current limit | VOUT = 0.85 × VOUT(NOM), VIN ≥ 3.3 V | 1100 | 1400 | 2000 | mA | ||
IGND | Ground pin current | IOUT = 1 mA | 60 | 100 | μA | |||
IOUT = 1 A | 350 | |||||||
ISHDN | Shutdown current (IGND) | VEN ≤ 0.4 V, VIN ≥ 2.2 V, RL = 1 kΩ, 0°C ≤ TJ ≤ 85°C |
0.2 | 2 | μA | |||
IFB | Feedback pin current | VIN = 6.5 V, VFB = 0.8 V | 0.02 | 1 | μA | |||
PSRR | Power-supply rejection ratio | VIN = 4.3 V, VOUT = 3.3 V, IOUT = 750 mA |
f = 100 Hz | 80 | dB | |||
f = 1 kHz | 82 | |||||||
f = 10 kHz | 78 | |||||||
f = 100 kHz | 60 | |||||||
f = 1 MHz | 54 | |||||||
Vn | Output noise voltage | BW = 100 Hz to 100 kHz, VIN = 3.8 V, VOUT = 3.3 V, IOUT = 100 mA, CNR = CBYPASS = 470 nF |
23.5 | μVRMS | ||||
VEN(HI) | Enable high (enabled) | 2.2 V ≤ VIN ≤ 3.6 V, RL = 1 kΩ | 1.2 | V | ||||
3.6 V < VIN ≤ 6.5 V, RL = 1 kΩ | 1.35 | |||||||
VEN(LO) | Enable low (shutdown) | RL = 1 kΩ | 0 | 0.4 | V | |||
IEN(HI) | Enable pin current, enabled | VIN = VEN = 6.5 V | 0.02 | 1 | μA | |||
tSTR | Start-up time | VOUT(NOM) = 3.3 V, VOUT = 0% to 90% VOUT(NOM), RL = 3.3 kΩ, COUT = 10 μF, CNR = 470 nF |
80 | ms | ||||
UVLO | Undervoltage lockout | VIN rising, RL = 1 kΩ | 1.86 | 2 | 2.10 | V | ||
Hysteresis | VIN falling, RL = 1 kΩ | 75 | mV | |||||
TSD | Thermal shutdown temperature | Shutdown, temperature increasing | 160 | °C | ||||
Reset, temperature decreasing | 140 | °C | ||||||
TJ | Operating junction temperature | –40 | 125 | °C |
NOTE: The Y-axis shows 1% VO per division | ||
VO = 0.8 V | IO = 750 mA | |
NOTE: The Y-axis shows 1% VO per division |
IO = 1 A | ||
IO = 500 mA | ||
VI = 3.6 V | ||
VO = VI – 0.5 V |
VI – VO = 1 V | C(IN) = 0 F | C(OUT) = 10 µF |
C(NR) = C(BYPASS) = 470 nF |
VI – VO = 1 V | C(IN) = 0 F | C(OUT) = 10 µF |
C(NR) = C(BYPASS) = 470 nF |
IO = 100 mA | C(IN) = 0 F |
VI – VO = 0.5 V | C(OUT) = 10 µF | C(IN) = 10 µF | |
24.09 µVRMS (C(NR) = C(BYPASS) = 100 nF) | |||
23.54 µVRMS (C(NR) = C(BYPASS) = 470 nF) |
23.54 µVRMS (IO = 100 mA) | C(IN) = 10 µF | VI – VO = 0.5 V |
23.71 µVRMS (IO = 750 mA) | C(NR) = 470 nF | C(OUT) = 10 µF |
22.78 µVRMS (IO = 1 A) | C(BYPASS) = 470 nF |
Using the same value of C(NR) and C(BYPASS) in the X-Axis |
IO = 100 mA → 1 A → 100 mA | ||
RL = 33 Ω | C(NR) = 470 nF | C(BYPASS) = 470 nF | ||
C(OUT) = 10 µF | C(IN) = 10 µF | |||
(1) The internal reference requires approximately 80 ms of rampup time (see Start-Up) from the enable event; therefore, VO fully reaches the target output voltage of 3.3 V in 80 ms from start-up. |
NOTE: The Y-axis shows 1% VO per division | ||
VO = 0.8 V | IO = 5 mA | |
NOTE: The Y-axis shows 1% VO per division |
IO = 750 mA | ||
VI = 3.6 V | ||
VO = 0.8 V | IO = 750 mA | |
V(EN) = 0.4 V | ||
C(NR) = C(BYPASS) = 470 nF | C(OUT) = 10 µF | C(IN) = 0 F |
VI – VO = 0.5 V | C(IN) = 0 F | C(OUT) = 10 µF |
C(NR) = C(BYPASS) = 470 nF |
VI – VO = 0.5 V | C(IN) = 0 F | C(OUT) = 10 µF |
C(NR) = C(BYPASS) = 470 nF |
IO = 750 mA | C(IN) = 0 F |
25.89 µVRMS (VO = 1.8 V) | C(IN) = 10 µF | VI – VO = 0.5 V |
23.54 µVRMS (VO = 2.5 V) | C(NR) = 470 nF | C(OUT) = 10 µF |
23.54 µVRMS (VO = 3.3 V) | C(BYPASS) = 470 nF |
23.54 µVRMS (CO = 10 µF) | C(IN) = 10 µF | VI – VO = 0.5 V |
23.91 µVRMS (CO = 22 µF) | C(NR) = 470 nF | C(OUT) = 10 µF |
22.78 µVRMS (CO = 100 µF) | C(BYPASS) = 470 nF |
VI = 3.8 V → 4.8 V → 3.8 V | ||
IO = 500 mA |
RL = 33 Ω | C(NR) = 470 nF | C(BYPASS) = 470 nF |
C(OUT) = 10 µF | C(IN) = 10 µF |
The TPS7A8101 device belongs to a family of new-generation LDO regulators that use innovative circuitry to achieve wide bandwidth and high loop gain, resulting in extremely high PSRR (over a 1-MHz range) even with very low headroom (VI – VO). A noise-reduction capacitor (C(NR)) at the NR pin and a bypass capacitor (C(BYPASS)) decrease noise generated by the bandgap reference to improve PSRR, while a quick-start circuit fast-charges the noise-reduction capacitor. This family of regulators offers sub-bandgap output voltages, current limit, and thermal protection, and is fully specified from –40°C to 125°C.
The TPS7A8101 internal current limit helps protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of output voltage. For reliable operation, the device should not be operated in a current limit state for extended periods of time.
The PMOS pass element in the TPS7A8101 has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting may be appropriate.
The enable pin (EN) is active high and is compatible with standard and low voltage, TTL-CMOS levels. When shutdown capability is not required, EN can be connected to IN.
Through a lower resistance, the bandgap reference can quickly charge the noise reduction capacitor (CNR). The TPS7A8101 has a quick-start circuit to quickly charge CNR, if present; see the . At start-up, this quick-start switch is closed, with only 33 kΩ of resistance between the bandgap reference and the NR pin. The quick-start switch opens approximately 100 ms after any device enabling event, and the resistance between the bandgap reference and the NR pin becomes higher in value (approximately 250 kΩ) to form a very good low-pass (RC) filter. This low-pass filter achieves very good noise reduction for the reference voltage.
Inrush current can be a problem in many applications. The 33-kΩ resistance during the start-up period is intentionally put there to slow down the reference voltage ramp up, thus reducing the inrush current. For example, the capacitance of connecting the recommended CNR value of 0.47 μF along with the 33-kΩ resistance causes approximately 80-ms RC delay. Start-up time with the other CNR values can be calculated as:
Although the noise reduction effect is nearly saturated at 0.47 μF, connecting a CNR value greater than 0.47 μF can help reduce noise slightly more; however, start-up time will be extremely long because the quick-start switch opens after approximately 100 ms. That is, if CNR is not fully charged during this 100-ms period, CNR finishes charging through a higher resistance of 250 kΩ, and takes much longer to fully charge.
A low leakage CNR should be used; most ceramic capacitors are suitable.
The TPS7A8101 uses an undervoltage lock-out circuit to keep the output shut off until the internal circuitry is operating properly. The UVLO circuit has a de-glitch feature so that it typically ignores undershoot transients on the input if they are less than 50-μs duration.
Driving the EN pin over 1.2 V for VI from 2.2 V to 3.6 V or 1.35 V for VI from 3.6 V to 6.5 V turns on the regulator. Driving the EN pin below 0.4 V causes the regulator to enter shutdown mode.
In shutdown, the current consumption of the device is reduced to 0.02 µA typically.